3 Commits

Author	SHA1	Message	Date
Flyinghead	cb8e81d473	arm64: direct memory access and jit rewrite ... generates direct vmem read & write accesses trap sigsegv and rewrite using slow path add w29 to allocatable registers get rid of literals and use pc-rel branching minor optimizations and cleanup	2019-01-16 13:04:16 +01:00
Flyinghead	ec7787c56a	vixl: enable debug log on android	2019-01-11 15:57:37 +01:00
Flyinghead	67a4eb8f1f	arm64 dynarec using vixl	2019-01-07 21:50:46 +01:00