375 lines
9.6 KiB
C++
375 lines
9.6 KiB
C++
/*
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Created on: Jun 5, 2019
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Copyright 2019 flyinghead
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This file is part of reicast.
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reicast is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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reicast is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with reicast. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "blockmanager.h"
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#include "ssa.h"
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#define SHIL_MODE 2
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#include "shil_canonical.h"
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void SSAOptimizer::InsertMov32Op(const shil_param& rd, const shil_param& rs)
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{
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shil_opcode op2(block->oplist[opnum]);
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op2.op = shop_mov32;
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op2.rd = rd;
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op2.rd2 = shil_param();
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op2.rs1 = rs;
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op2.rs2 = shil_param();
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op2.rs3 = shil_param();
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block->oplist.insert(block->oplist.begin() + opnum + 1, op2);
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opnum++;
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}
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bool SSAOptimizer::ExecuteConstOp(shil_opcode* op)
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{
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if (!op->rs1.is_reg() && !op->rs2.is_reg() && !op->rs3.is_reg()
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&& (op->rs1.is_imm() || op->rs2.is_imm() || op->rs3.is_imm())
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&& op->rd.is_reg())
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{
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// Only immediate operands -> execute the op at compile time
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u32 rs1 = op->rs1.is_imm() ? op->rs1.imm_value() : 0;
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u32 rs2 = op->rs2.is_imm() ? op->rs2.imm_value() : 0;
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u32 rs3 = op->rs3.is_imm() ? op->rs3.imm_value() : 0;
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u32 rd;
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u32 rd2;
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switch (op->op)
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{
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case shop_mov32:
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rd = rs1;
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break;
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case shop_add:
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rd = shil_opcl_add::f1::impl(rs1, rs2);
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break;
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case shop_sub:
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rd = shil_opcl_sub::f1::impl(rs1, rs2);
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break;
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case shop_adc:
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case shop_sbc:
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case shop_negc:
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case shop_rocl:
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case shop_rocr:
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{
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u64 v;
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if (op->op == shop_adc)
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v = shil_opcl_adc::f1::impl(rs1, rs2, rs3);
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else if (op->op == shop_sbc)
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v = shil_opcl_sbc::f1::impl(rs1, rs2, rs3);
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else if (op->op == shop_rocl)
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v = shil_opcl_rocl::f1::impl(rs1, rs2);
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else if (op->op == shop_rocr)
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v = shil_opcl_rocr::f1::impl(rs1, rs2);
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else
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v = shil_opcl_negc::f1::impl(rs1, rs2);
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rd = (u32)v;
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rd2 = (u32)(v >> 32);
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shil_param op2_rd = shil_param(op->rd2._reg);
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op2_rd.version[0] = op->rd2.version[0];
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InsertMov32Op(op2_rd, shil_param(FMT_IMM, rd2));
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// the previous insert might have invalidated our reference
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op = &block->oplist[opnum - 1];
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op->rd2 = shil_param();
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}
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break;
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case shop_shl:
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rd = shil_opcl_shl::f1::impl(rs1, rs2);
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break;
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case shop_shr:
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rd = shil_opcl_shr::f1::impl(rs1, rs2);
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break;
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case shop_sar:
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rd = shil_opcl_sar::f1::impl(rs1, rs2);
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break;
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case shop_ror:
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rd = shil_opcl_ror::f1::impl(rs1, rs2);
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break;
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case shop_shld:
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rd = shil_opcl_shld::f1::impl(rs1, rs2);
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break;
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case shop_shad:
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rd = shil_opcl_shad::f1::impl(rs1, rs2);
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break;
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case shop_or:
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rd = shil_opcl_or::f1::impl(rs1, rs2);
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break;
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case shop_and:
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rd = shil_opcl_and::f1::impl(rs1, rs2);
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break;
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case shop_xor:
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rd = shil_opcl_xor::f1::impl(rs1, rs2);
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break;
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case shop_not:
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rd = shil_opcl_not::f1::impl(rs1);
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break;
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case shop_ext_s16:
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rd = shil_opcl_ext_s16::f1::impl(rs1);
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break;
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case shop_ext_s8:
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rd = shil_opcl_ext_s8::f1::impl(rs1);
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break;
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case shop_mul_i32:
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rd = shil_opcl_mul_i32::f1::impl(rs1, rs2);
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break;
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case shop_mul_u16:
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rd = shil_opcl_mul_u16::f1::impl(rs1, rs2);
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break;
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case shop_mul_s16:
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rd = shil_opcl_mul_s16::f1::impl(rs1, rs2);
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break;
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case shop_mul_u64:
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case shop_mul_s64:
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{
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u64 v;
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if (op->op == shop_mul_u64)
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v = shil_opcl_mul_u64::f1::impl(rs1, rs2);
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else
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v = shil_opcl_mul_s64::f1::impl(rs1, rs2);
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rd = (u32)v;
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rd2 = (u32)(v >> 32);
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shil_param op2_rd = shil_param(op->rd2._reg);
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op2_rd.version[0] = op->rd2.version[0];
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InsertMov32Op(op2_rd, shil_param(FMT_IMM, rd2));
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// the previous insert might have invalidated our reference
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op = &block->oplist[opnum - 1];
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op->rd2 = shil_param();
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}
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break;
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case shop_test:
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rd = shil_opcl_test::f1::impl(rs1, rs2);
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break;
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case shop_neg:
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rd = shil_opcl_neg::f1::impl(rs1);
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break;
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case shop_swaplb:
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rd = shil_opcl_swaplb::f1::impl(rs1);
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break;
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case shop_swap:
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rd = shil_opcl_swap::f1::impl(rs1);
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break;
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case shop_seteq:
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rd = shil_opcl_seteq::f1::impl(rs1, rs2);
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break;
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case shop_setgt:
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rd = shil_opcl_setgt::f1::impl(rs1, rs2);
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break;
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case shop_setge:
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rd = shil_opcl_setge::f1::impl(rs1, rs2);
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break;
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case shop_setab:
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rd = shil_opcl_setab::f1::impl(rs1, rs2);
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break;
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case shop_setae:
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rd = shil_opcl_setae::f1::impl(rs1, rs2);
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break;
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case shop_setpeq:
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rd = shil_opcl_setpeq::f1::impl(rs1, rs2);
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break;
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case shop_xtrct:
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rd = shil_opcl_xtrct::f1::impl(rs1, rs2);
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break;
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case shop_div32u:
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case shop_div32s:
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{
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u64 res = op->op == shop_div32u ? shil_opcl_div32u::f1::impl(rs1, rs2, rs3) : shil_opcl_div32s::f1::impl(rs1, rs2, rs3);
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rd = (u32)res;
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constprop_values[RegValue(op->rd, 1)] = res >> 32;
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shil_param op2_rd = shil_param((Sh4RegType)(op->rd._reg + 1));
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op2_rd.version[0] = op->rd.version[1];
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InsertMov32Op(op2_rd, shil_param(FMT_IMM, res >> 32));
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// the previous insert might have invalidated our reference
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op = &block->oplist[opnum - 1];
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}
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break;
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case shop_div32p2:
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rd = shil_opcl_div32p2::f1::impl(rs1, rs2, rs3);
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break;
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case shop_jdyn:
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{
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verify(BET_GET_CLS(block->BlockType) == BET_CLS_Dynamic);
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rs1 += rs2;
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switch ((block->BlockType >> 1) & 3)
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{
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case BET_SCL_Jump:
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case BET_SCL_Ret:
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block->BlockType = BET_StaticJump;
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block->BranchBlock = rs1;
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break;
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case BET_SCL_Call:
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block->BlockType = BET_StaticCall;
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block->BranchBlock = rs1;
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break;
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case BET_SCL_Intr:
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block->BlockType = BET_StaticIntr;
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block->NextBlock = rs1;
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break;
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default:
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die("Unexpected block end type\n")
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;
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}
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// rd (that is jdyn) won't be updated but since it's not a real register
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// it shouldn't be a problem
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block->oplist.erase(block->oplist.begin() + opnum);
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opnum--;
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stats.dyn_to_stat_blocks++;
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return true;
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}
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case shop_jcond:
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{
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if (rs1 != (block->BlockType & 1))
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{
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block->BranchBlock = block->NextBlock;
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}
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block->BlockType = BET_StaticJump;
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block->NextBlock = NullAddress;
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block->has_jcond = false;
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// same remark regarding jdyn as in the previous case
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block->oplist.erase(block->oplist.begin() + opnum);
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opnum--;
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stats.dyn_to_stat_blocks++;
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return true;
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}
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case shop_fneg:
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{
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f32 frd = shil_opcl_fneg::f1::impl(reinterpret_cast<f32&>(rs1));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fadd:
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{
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f32 frd = shil_opcl_fadd::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fsub:
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{
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f32 frd = shil_opcl_fsub::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fmul:
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{
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f32 frd = shil_opcl_fmul::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fdiv:
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{
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f32 frd = shil_opcl_fdiv::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_cvt_i2f_n:
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{
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f32 frd = shil_opcl_cvt_i2f_n::f1::impl(rs1);
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_cvt_i2f_z:
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{
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f32 frd = shil_opcl_cvt_i2f_z::f1::impl(rs1);
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fsqrt:
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{
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f32 frd = shil_opcl_fsqrt::f1::impl(reinterpret_cast<f32&>(rs1));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_cvt_f2i_t:
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{
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f32 r1 = reinterpret_cast<f32&>(rs1);
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rd = shil_opcl_cvt_f2i_t::f1::impl(r1);
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}
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break;
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case shop_fsrra:
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{
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f32 frd = shil_opcl_fsrra::f1::impl(reinterpret_cast<f32&>(rs1));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fsca:
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{
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f32 tmp[2];
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shil_opcl_fsca::fsca_table::impl(tmp, rs1);
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rd = reinterpret_cast<u32&>(tmp[0]);
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u32 rd_1 = reinterpret_cast<u32&>(tmp[1]);
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constprop_values[RegValue(op->rd, 1)] = rd_1;
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shil_param op2_rd = shil_param((Sh4RegType)(op->rd._reg + 1));
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op2_rd.version[0] = op->rd.version[1];
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InsertMov32Op(op2_rd, shil_param(FMT_IMM, rd_1));
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// the previous insert might have invalidated our reference
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op = &block->oplist[opnum - 1];
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op->rd.type = FMT_F32;
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}
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break;
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case shop_fabs:
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{
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f32 frd = shil_opcl_fabs::f1::impl(reinterpret_cast<f32&>(rs1));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fmac:
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{
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f32 frd = shil_opcl_fmac::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2), reinterpret_cast<f32&>(rs3));
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rd = reinterpret_cast<u32&>(frd);
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}
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break;
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case shop_fseteq:
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rd = shil_opcl_fseteq::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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break;
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case shop_fsetgt:
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rd = shil_opcl_fsetgt::f1::impl(reinterpret_cast<f32&>(rs1), reinterpret_cast<f32&>(rs2));
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break;
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default:
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ERROR_LOG(DYNAREC, "unhandled constant op %d", op->op);
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die("unhandled constant op");
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break;
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}
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constprop_values[RegValue(op->rd)] = rd;
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if (op->rd2.is_r32())
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constprop_values[RegValue(op->rd2)] = rd2;
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ReplaceByMov32(*op, rd);
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return true;
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}
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else
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{
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return false;
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}
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}
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