..
dyna
net rollback with ggpo
2021-09-02 17:51:23 +02:00
interpr
fix sh4 scheduler. use common cycle counter in sh4 context
2021-10-07 16:18:32 +02:00
modules
New serialize framework. Delay maple dma xfer
2021-11-13 15:56:42 +01:00
fsca-table.h
Moving code around, cleanups
2013-12-28 22:20:08 +01:00
sh4_cache.h
New serialize framework. Delay maple dma xfer
2021-11-13 15:56:42 +01:00
sh4_core.h
mmu: add address cache to mem slow path. better fastmmu hashtable.
2021-05-14 19:03:57 +02:00
sh4_core_regs.cpp
arm32: replace old arm emitter with vixl
2021-05-15 11:41:00 +02:00
sh4_if.h
fix sh4 scheduler. use common cycle counter in sh4 context
2021-10-07 16:18:32 +02:00
sh4_interpreter.h
fix sh4 scheduler. use common cycle counter in sh4 context
2021-10-07 16:18:32 +02:00
sh4_interrupts.cpp
naomi: close cart on reset. sh4: replace some verify by throw
2021-08-03 09:47:13 +02:00
sh4_interrupts.h
clang-tidy: run readability-inconsistent-declaration-parameter-name and improve parameter names
2021-03-15 19:52:54 +01:00
sh4_mem.cpp
cheats: support for bit-level RA codes
2021-10-12 17:28:01 +02:00
sh4_mem.h
mmu: add address cache to mem slow path. better fastmmu hashtable.
2021-05-14 19:03:57 +02:00
sh4_mmr.cpp
cheats: support for bit-level RA codes
2021-10-12 17:28:01 +02:00
sh4_mmr.h
area 7 access to sh4 mm registers only through mmu translation
2021-04-01 13:30:37 +02:00
sh4_opcode_list.cpp
dynarec: fix CLRS and SETS ops
2021-11-11 10:44:22 +01:00
sh4_opcode_list.h
rename and clean up
2019-08-30 23:35:10 +02:00
sh4_rom.cpp
Split CFLAGS/CXXFLAGS on core.mk, warning fixes
2014-05-12 20:53:43 +03:00
sh4_rom.h
Moving code around, cleanups
2013-12-28 22:20:08 +01:00
sh4_sched.cpp
fix sh4 scheduler. use common cycle counter in sh4 context
2021-10-07 16:18:32 +02:00
sh4_sched.h
fix sh4 scheduler. use common cycle counter in sh4 context
2021-10-07 16:18:32 +02:00