Flyinghead 673c2988d6 libretro: backport libnx support. Fix log source paths		2021-07-07 19:01:37 +02:00
..
dyna	libretro: backport libnx support. Fix log source paths	2021-07-07 19:01:37 +02:00
interpr	Misc cleanup	2021-06-06 11:15:06 +02:00
modules	Misc cleanup	2021-06-06 11:15:06 +02:00
fsca-table.h	Moving code around, cleanups	2013-12-28 22:20:08 +01:00
sh4_cache.h	area 7 access to sh4 mm registers only through mmu translation	2021-04-01 13:30:37 +02:00
sh4_core.h	mmu: add address cache to mem slow path. better fastmmu hashtable.	2021-05-14 19:03:57 +02:00
sh4_core_regs.cpp	arm32: replace old arm emitter with vixl	2021-05-15 11:41:00 +02:00
sh4_if.h	wince: ditch vmem32. use address LUT in dynarec. finer grained flush	2021-05-17 11:59:34 +02:00
sh4_interpreter.h	arm32: replace old arm emitter with vixl	2021-05-15 11:41:00 +02:00
sh4_interrupts.cpp	Misc cleanup	2021-06-06 11:15:06 +02:00
sh4_interrupts.h	clang-tidy: run readability-inconsistent-declaration-parameter-name and improve parameter names	2021-03-15 19:52:54 +01:00
sh4_mem.cpp	mmu: add address cache to mem slow path. better fastmmu hashtable.	2021-05-14 19:03:57 +02:00
sh4_mem.h	mmu: add address cache to mem slow path. better fastmmu hashtable.	2021-05-14 19:03:57 +02:00
sh4_mmr.cpp	mmu: add address cache to mem slow path. better fastmmu hashtable.	2021-05-14 19:03:57 +02:00
sh4_mmr.h	area 7 access to sh4 mm registers only through mmu translation	2021-04-01 13:30:37 +02:00
sh4_opcode_list.cpp	sh4: promote opcode 0 as regular NOP	2020-11-21 20:06:59 +01:00
sh4_opcode_list.h	rename and clean up	2019-08-30 23:35:10 +02:00
sh4_rom.cpp	Split CFLAGS/CXXFLAGS on core.mk, warning fixes	2014-05-12 20:53:43 +03:00
sh4_rom.h	Moving code around, cleanups	2013-12-28 22:20:08 +01:00
sh4_sched.cpp	Misc cleanup	2021-06-06 11:15:06 +02:00
sh4_sched.h	Cleanup compiler warnings (mostly sign-compare)	2020-03-30 23:00:43 +02:00