527 lines
15 KiB
C++
527 lines
15 KiB
C++
/*
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Dreamcast 'area 0' emulation
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Pretty much all peripheral registers are mapped here
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Routing is mostly handled here, as well as flash/SRAM emulation
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*/
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#include "sb_mem.h"
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#include "sb.h"
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#include "hw/aica/aica_if.h"
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#include "hw/flashrom/flashrom.h"
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#include "hw/gdrom/gdrom_if.h"
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#include "hw/modem/modem.h"
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#include "hw/naomi/naomi.h"
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#include "hw/pvr/pvr_mem.h"
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#include "hw/sh4/sh4_mem.h"
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#include "reios/reios.h"
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MemChip *sys_rom;
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MemChip *sys_nvmem;
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extern bool bios_loaded;
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static std::string getRomPrefix()
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{
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switch (settings.platform.system)
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{
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case DC_PLATFORM_DREAMCAST:
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return "dc_";
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case DC_PLATFORM_NAOMI:
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return "naomi_";
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case DC_PLATFORM_ATOMISWAVE:
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return "aw_";
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default:
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die("Unsupported platform");
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return "";
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}
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}
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static void add_isp_to_nvmem(DCFlashChip *flash)
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{
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u8 block[64];
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if (!flash->ReadBlock(FLASH_PT_USER, FLASH_USER_INET, block))
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{
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memset(block, 0, sizeof(block));
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strcpy((char *)block + 2, "PWBrowser");
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block[12] = 0x1c;
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_INET, block);
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memset(block, 0, sizeof(block));
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_INET + 1, block);
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strcpy((char *)block + 32, "AT&F");
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_INET + 2, block);
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memset(block, 0, sizeof(block));
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_INET + 3, block);
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memset(block + 27, 0xFF, sizeof(block) - 27);
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block[10] = 1;
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block[14] = 1;
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block[16] = 1;
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block[19] = 6;
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block[26] = 5;
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_INET + 4, block);
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memset(block, 0xFF, sizeof(block));
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for (u32 i = FLASH_USER_INET + 5; i <= 0xbf; i++)
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flash->WriteBlock(FLASH_PT_USER, i, block);
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flash_isp1_block isp1;
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memset(&isp1, 0, sizeof(isp1));
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isp1._unknown[3] = 1;
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memcpy(isp1.sega, "SEGA", 4);
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strcpy(isp1.username, "flycast1");
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strcpy(isp1.password, "password");
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strcpy(isp1.phone, "1234567");
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if (flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1, &isp1) != 1)
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WARN_LOG(FLASHROM, "Failed to save ISP information to flash RAM");
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memset(block, 0, sizeof(block));
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1 + 1, block);
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1 + 2, block);
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1 + 3, block);
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1 + 4, block);
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block[60] = 1;
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flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP1 + 5, block);
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flash_isp2_block isp2;
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memset(&isp2, 0, sizeof(isp2));
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memcpy(isp2.sega, "SEGA", 4);
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strcpy(isp2.username, "flycast2");
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strcpy(isp2.password, "password");
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strcpy(isp2.phone, "1234567");
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if (flash->WriteBlock(FLASH_PT_USER, FLASH_USER_ISP2, &isp2) != 1)
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WARN_LOG(FLASHROM, "Failed to save ISP information to flash RAM");
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u8 block[64];
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memset(block, 0, sizeof(block));
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for (u32 i = FLASH_USER_ISP2 + 1; i <= 0xEA; i++)
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{
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if (i == 0xcb)
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block[56] = 1;
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else
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block[56] = 0;
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flash->WriteBlock(FLASH_PT_USER, i, block);
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}
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}
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}
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void FixUpFlash()
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{
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if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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{
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static_cast<DCFlashChip*>(sys_nvmem)->Validate();
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// overwrite factory flash settings
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if (settings.dreamcast.region <= 2)
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{
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sys_nvmem->data[0x1a002] = '0' + settings.dreamcast.region;
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sys_nvmem->data[0x1a0a2] = '0' + settings.dreamcast.region;
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}
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if (settings.dreamcast.language <= 5)
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{
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sys_nvmem->data[0x1a003] = '0' + settings.dreamcast.language;
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sys_nvmem->data[0x1a0a3] = '0' + settings.dreamcast.language;
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}
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if (settings.dreamcast.broadcast <= 3)
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{
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sys_nvmem->data[0x1a004] = '0' + settings.dreamcast.broadcast;
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sys_nvmem->data[0x1a0a4] = '0' + settings.dreamcast.broadcast;
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}
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// overwrite user settings
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struct flash_syscfg_block syscfg;
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int res = static_cast<DCFlashChip*>(sys_nvmem)->ReadBlock(FLASH_PT_USER, FLASH_USER_SYSCFG, &syscfg);
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if (!res)
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{
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// write out default settings
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memset(&syscfg, 0xff, sizeof(syscfg));
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syscfg.time_lo = 0;
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syscfg.time_hi = 0;
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syscfg.lang = 0;
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syscfg.mono = 0;
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syscfg.autostart = 1;
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}
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u32 now = GetRTC_now();
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syscfg.time_lo = now & 0xffff;
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syscfg.time_hi = now >> 16;
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if (settings.dreamcast.language <= 5)
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syscfg.lang = settings.dreamcast.language;
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if (static_cast<DCFlashChip*>(sys_nvmem)->WriteBlock(FLASH_PT_USER, FLASH_USER_SYSCFG, &syscfg) != 1)
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WARN_LOG(FLASHROM, "Failed to save time and language to flash RAM");
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add_isp_to_nvmem(static_cast<DCFlashChip*>(sys_nvmem));
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// Check the console ID used by some network games (chuchu rocket)
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u8 *console_id = &sys_nvmem->data[0x1A058];
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if (!memcmp(console_id, "\377\377\377\377\377\377", 6))
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{
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srand(now);
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for (int i = 0; i < 6; i++)
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{
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console_id[i] = rand();
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console_id[i + 0xA0] = console_id[i]; // copy at 1A0F8
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}
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}
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}
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}
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static bool nvmem_load(const std::string& root)
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{
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bool rc;
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if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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rc = sys_nvmem->Load(root, getRomPrefix(), "%nvmem.bin", "nvram");
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else
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rc = sys_nvmem->Load(get_game_save_prefix() + ".nvmem");
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if (!rc)
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INFO_LOG(FLASHROM, "flash/nvmem is missing, will create new file...");
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if (settings.platform.system == DC_PLATFORM_ATOMISWAVE)
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sys_rom->Load(get_game_save_prefix() + ".nvmem2");
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return true;
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}
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bool LoadRomFiles(const std::string& root)
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{
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nvmem_load(root);
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if (settings.platform.system != DC_PLATFORM_ATOMISWAVE)
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{
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if (sys_rom->Load(root, getRomPrefix(), "%boot.bin;%boot.bin.bin;%bios.bin;%bios.bin.bin", "bootrom"))
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bios_loaded = true;
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else if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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return false;
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}
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return true;
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}
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void SaveRomFiles(const std::string& root)
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{
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if (settings.platform.system == DC_PLATFORM_DREAMCAST)
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sys_nvmem->Save(root, getRomPrefix(), "nvmem.bin", "nvmem");
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else
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sys_nvmem->Save(get_game_save_prefix() + ".nvmem");
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if (settings.platform.system == DC_PLATFORM_ATOMISWAVE)
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sys_rom->Save(get_game_save_prefix() + ".nvmem2");
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}
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bool LoadHle(const std::string& root)
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{
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if (!nvmem_load(root))
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WARN_LOG(FLASHROM, "No nvmem loaded\n");
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reios_reset(sys_rom->data);
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return true;
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}
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static u32 ReadFlash(u32 addr,u32 sz) { return sys_nvmem->Read(addr,sz); }
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static void WriteFlash(u32 addr,u32 data,u32 sz) { sys_nvmem->Write(addr,data,sz); }
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static u32 ReadBios(u32 addr,u32 sz)
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{
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return sys_rom->Read(addr, sz);
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}
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static void WriteBios(u32 addr,u32 data,u32 sz)
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{
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if (settings.platform.system == DC_PLATFORM_ATOMISWAVE)
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{
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if (sz != 1)
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{
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INFO_LOG(MEMORY, "Invalid access size @%08x data %x sz %d", addr, data, sz);
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return;
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}
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sys_rom->Write(addr, data, sz);
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}
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else
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{
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INFO_LOG(MEMORY, "Write to [Boot ROM] is not possible, addr=%x, data=%x, size=%d", addr, data, sz);
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}
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}
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//Area 0 mem map
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//0x00000000- 0x001FFFFF :MPX System/Boot ROM
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//0x00200000- 0x0021FFFF :Flash Memory
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//0x00400000- 0x005F67FF :Unassigned
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//0x005F6800- 0x005F69FF :System Control Reg.
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//0x005F6C00- 0x005F6CFF :Maple i/f Control Reg.
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//0x005F7000- 0x005F70FF :GD-ROM / NAOMI BD Reg.
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//0x005F7400- 0x005F74FF :G1 i/f Control Reg.
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//0x005F7800- 0x005F78FF :G2 i/f Control Reg.
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//0x005F7C00- 0x005F7CFF :PVR i/f Control Reg.
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//0x005F8000- 0x005F9FFF :TA / PVR Core Reg.
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//0x00600000- 0x006007FF :MODEM
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//0x00600800- 0x006FFFFF :G2 (Reserved)
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//0x00700000- 0x00707FFF :AICA- Sound Cntr. Reg.
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//0x00710000- 0x0071000B :AICA- RTC Cntr. Reg.
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//0x00800000- 0x00FFFFFF :AICA- Wave Memory
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//0x01000000- 0x01FFFFFF :Ext. Device
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//0x02000000- 0x03FFFFFF* :Image Area* 2MB
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//use unified size handler for registers
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//it really makes no sense to use different size handlers on em -> especially when we can use templates :p
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template<class T>
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T DYNACALL ReadMem_area0(u32 addr)
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{
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constexpr u32 sz = (u32)sizeof(T);
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addr &= 0x01FFFFFF;//to get rid of non needed bits
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const u32 base=(addr>>16);
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//map 0x0000 to 0x01FF to Default handler
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//mirror 0x0200 to 0x03FF , from 0x0000 to 0x03FFF
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//map 0x0000 to 0x001F
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// :MPX System/Boot ROM
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if (base <= (settings.platform.system == DC_PLATFORM_ATOMISWAVE ? 0x0001 : 0x001F)) // Only 128k BIOS on AtomisWave
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{
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return ReadBios(addr,sz);
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}
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//map 0x0020 to 0x0021
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else if ((base>= 0x0020) && (base<= 0x0021)) // :Flash Memory
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{
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return ReadFlash(addr&0x1FFFF,sz);
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}
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//map 0x005F to 0x005F
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else if (likely(base==0x005F))
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{
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if (addr <= 0x005F67FF) // :Unassigned
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{
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INFO_LOG(MEMORY, "Read from area0_32 not implemented [Unassigned], addr=%x", addr);
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return 0;
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}
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else if (addr >= 0x005F7000 && addr <= 0x005F70FF) // GD-ROM
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{
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if (settings.platform.system != DC_PLATFORM_DREAMCAST)
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return (T)ReadMem_naomi(addr, sz);
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else
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return (T)ReadMem_gdrom(addr, sz);
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}
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else if (likely(addr >= 0x005F6800 && addr <= 0x005F7CFF)) // /*:PVR i/f Control Reg.*/ -> ALL SB registers now
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{
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return (T)sb_ReadMem(addr,sz);
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}
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else if (likely(addr >= 0x005F8000 && addr <= 0x005F9FFF)) // :TA / PVR Core Reg.
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{
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if (sz != 4)
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// House of the Dead 2
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return 0;
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return (T)pvr_ReadReg(addr);
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}
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}
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//map 0x0060 to 0x0060
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else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // :MODEM
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{
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if (settings.platform.system != DC_PLATFORM_DREAMCAST)
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return (T)libExtDevice_ReadMem_A0_006(addr, sz);
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else
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#if defined(ENABLE_MODEM)
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return (T)ModemReadMem_A0_006(addr, sz);
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#else
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return (T)0;
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#endif
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}
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//map 0x0060 to 0x006F
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else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // :G2 (Reserved)
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{
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INFO_LOG(COMMON, "Read from area0_32 not implemented [G2 (Reserved)], addr=%x", addr);
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return 0;
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}
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//map 0x0070 to 0x0070
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else if ((base ==0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // :AICA- Sound Cntr. Reg.
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{
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return (T)ReadMem_aica_reg(addr, sz);
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}
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//map 0x0071 to 0x0071
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else if ((base ==0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // :AICA- RTC Cntr. Reg.
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{
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return (T)ReadMem_aica_rtc(addr,sz);
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}
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//map 0x0080 to 0x00FF
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else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // :AICA- Wave Memory
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{
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ReadMemArrRet(aica_ram.data,addr&ARAM_MASK,sz);
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}
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//map 0x0100 to 0x01FF
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else if (base >= 0x0100 && base <= 0x01FF) // G2 Ext. Device #1
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{
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if (settings.platform.system == DC_PLATFORM_NAOMI)
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return (T)libExtDevice_ReadMem_A0_010(addr, sz);
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else
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{
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INFO_LOG(MEMORY, "Read from BBA not implemented, addr=%x", addr);
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return 0;
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}
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}
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INFO_LOG(MEMORY, "Read from area0<%d> not implemented [Unassigned], addr=%x", sz, addr);
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return 0;
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}
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template<class T>
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void DYNACALL WriteMem_area0(u32 addr,T data)
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{
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constexpr u32 sz = (u32)sizeof(T);
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addr &= 0x01FFFFFF;//to get rid of non needed bits
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const u32 base=(addr>>16);
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//map 0x0000 to 0x001F
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// :MPX System/Boot ROM
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if (base <= (settings.platform.system == DC_PLATFORM_ATOMISWAVE ? 0x0001 : 0x001F)) // Only 128k BIOS on AtomisWave
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{
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WriteBios(addr,data,sz);
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}
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//map 0x0020 to 0x0021
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else if ((base >=0x0020) && (base <=0x0021) /*&& (addr>= 0x00200000) && (addr<= 0x0021FFFF)*/) // Flash Memory
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{
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WriteFlash(addr,data,sz);
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}
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//map 0x0040 to 0x005F -> actually, I'll only map 0x005F to 0x005F, b/c the rest of it is unspammed (left to default handler)
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//map 0x005F to 0x005F
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else if ( likely(base==0x005F) )
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{
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if (addr <= 0x005F67FF) // Unassigned
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{
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INFO_LOG(COMMON, "Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d", addr, data, sz);
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}
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else if (addr >= 0x005F7000 && addr <= 0x005F70FF) // GD-ROM
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{
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if (settings.platform.system != DC_PLATFORM_DREAMCAST)
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WriteMem_naomi(addr,data,sz);
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else
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WriteMem_gdrom(addr,data,sz);
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}
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else if ( likely((addr>= 0x005F6800) && (addr<=0x005F7CFF)) ) // /*:PVR i/f Control Reg.*/ -> ALL SB registers
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{
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sb_WriteMem(addr,data,sz);
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}
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else if ( likely((addr>= 0x005F8000) && (addr<=0x005F9FFF)) ) // TA / PVR Core Reg.
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{
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verify(sz==4);
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pvr_WriteReg(addr,data);
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}
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else
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INFO_LOG(COMMON, "Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d", addr, data, sz);
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}
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//map 0x0060 to 0x0060
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else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // MODEM
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{
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if (settings.platform.system != DC_PLATFORM_DREAMCAST)
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libExtDevice_WriteMem_A0_006(addr, data, sz);
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#if defined(ENABLE_MODEM)
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else
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ModemWriteMem_A0_006(addr, data, sz);
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#endif
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}
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//map 0x0060 to 0x006F
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else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // G2 (Reserved)
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{
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INFO_LOG(COMMON, "Write to area0_32 not implemented [G2 (Reserved)], addr=%x,data=%x,size=%d", addr, data, sz);
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}
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//map 0x0070 to 0x0070
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else if ((base >=0x0070) && (base <=0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // AICA- Sound Cntr. Reg.
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{
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WriteMem_aica_reg(addr,data,sz);
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}
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//map 0x0071 to 0x0071
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else if ((base >=0x0071) && (base <=0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // AICA- RTC Cntr. Reg.
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{
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WriteMem_aica_rtc(addr,data,sz);
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}
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//map 0x0080 to 0x00FF
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else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // AICA- Wave Memory
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{
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WriteMemArr(aica_ram.data, addr & ARAM_MASK, data, sz);
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}
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//map 0x0100 to 0x01FF
|
|
else if (base >= 0x0100 && base <= 0x01FF) // G2 Ext. Device #1
|
|
{
|
|
if (settings.platform.system == DC_PLATFORM_NAOMI)
|
|
libExtDevice_WriteMem_A0_010(addr, data, sz);
|
|
else
|
|
INFO_LOG(COMMON, "Write to BBA not implemented, addr=%x, data=%x, size=%d", addr, data, sz);
|
|
}
|
|
else
|
|
INFO_LOG(COMMON, "Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d", addr, data, sz);
|
|
}
|
|
|
|
//Init/Res/Term
|
|
void sh4_area0_Init()
|
|
{
|
|
sb_Init();
|
|
}
|
|
|
|
void sh4_area0_Reset(bool hard)
|
|
{
|
|
if (hard)
|
|
{
|
|
if (sys_rom != NULL)
|
|
{
|
|
delete sys_rom;
|
|
sys_rom = NULL;
|
|
}
|
|
if (sys_nvmem != NULL)
|
|
{
|
|
delete sys_nvmem;
|
|
sys_nvmem = NULL;
|
|
}
|
|
|
|
switch (settings.platform.system)
|
|
{
|
|
case DC_PLATFORM_DREAMCAST:
|
|
sys_rom = new RomChip(settings.platform.bios_size);
|
|
sys_nvmem = new DCFlashChip(settings.platform.flash_size);
|
|
reios_set_flash(sys_nvmem);
|
|
break;
|
|
case DC_PLATFORM_NAOMI:
|
|
sys_rom = new RomChip(settings.platform.bios_size);
|
|
sys_nvmem = new SRamChip(settings.platform.bbsram_size);
|
|
break;
|
|
case DC_PLATFORM_ATOMISWAVE:
|
|
sys_rom = new DCFlashChip(settings.platform.bios_size, settings.platform.bios_size / 2);
|
|
sys_nvmem = new SRamChip(settings.platform.bbsram_size);
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
sys_rom->Reset();
|
|
sys_nvmem->Reset();
|
|
}
|
|
sb_Reset(hard);
|
|
}
|
|
|
|
void sh4_area0_Term()
|
|
{
|
|
if (sys_rom != NULL)
|
|
{
|
|
delete sys_rom;
|
|
sys_rom = NULL;
|
|
}
|
|
if (sys_nvmem != NULL)
|
|
{
|
|
delete sys_nvmem;
|
|
sys_nvmem = NULL;
|
|
}
|
|
sb_Term();
|
|
}
|
|
|
|
|
|
//AREA 0
|
|
static _vmem_handler area0_handler;
|
|
|
|
|
|
void map_area0_init()
|
|
{
|
|
|
|
area0_handler = _vmem_register_handler_Template(ReadMem_area0,WriteMem_area0);
|
|
}
|
|
void map_area0(u32 base)
|
|
{
|
|
verify(base<0xE0);
|
|
|
|
_vmem_map_handler(area0_handler,0x00|base,0x01|base);
|
|
|
|
//0x0240 to 0x03FF mirrors 0x0040 to 0x01FF (no flashrom or bios)
|
|
//0x0200 to 0x023F are unused
|
|
_vmem_mirror_mapping(0x02|base,0x00|base,0x02);
|
|
}
|