472 lines
10 KiB
C++
472 lines
10 KiB
C++
/*
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aica interface
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Handles RTC, Display mode reg && arm reset reg !
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arm7 is handled on a separate arm plugin now
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*/
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#include "aica_if.h"
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#include "aica_mem.h"
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#include "hw/holly/sb.h"
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#include "hw/holly/holly_intc.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/sh4/sh4_sched.h"
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#include "profiler/profiler.h"
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#include "hw/sh4/dyna/blockmanager.h"
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#include "hw/arm7/arm7.h"
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#include <ctime>
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VArray2 aica_ram;
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u32 VREG;
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u32 ARMRST;
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u32 rtc_EN;
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int dma_sched_id;
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u32 RealTimeClock;
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int rtc_schid = -1;
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u32 GetRTC_now()
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{
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// The Dreamcast Epoch time is 1/1/50 00:00 but without support for time zone or DST.
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// We compute the TZ/DST current time offset and add it to the result
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// as if we were in the UTC time zone (as well as the DC Epoch)
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time_t rawtime = time(NULL);
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struct tm localtm, gmtm;
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localtm = *localtime(&rawtime);
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gmtm = *gmtime(&rawtime);
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gmtm.tm_isdst = -1;
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time_t time_offset = mktime(&localtm) - mktime(&gmtm);
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// 1/1/50 to 1/1/70 is 20 years and 5 leap days
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return (20 * 365 + 5) * 24 * 60 * 60 + rawtime + time_offset;
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}
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u32 ReadMem_aica_rtc(u32 addr,u32 sz)
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{
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switch( addr & 0xFF )
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{
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case 0:
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return RealTimeClock>>16;
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case 4:
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return RealTimeClock &0xFFFF;
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case 8:
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return 0;
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}
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WARN_LOG(AICA, "ReadMem_aica_rtc : invalid address %x sz %d", addr, sz);
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return 0;
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}
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void WriteMem_aica_rtc(u32 addr,u32 data,u32 sz)
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{
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switch( addr & 0xFF )
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{
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case 0:
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if (rtc_EN)
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{
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RealTimeClock&=0xFFFF;
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RealTimeClock|=(data&0xFFFF)<<16;
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rtc_EN=0;
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}
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return;
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case 4:
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if (rtc_EN)
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{
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RealTimeClock&=0xFFFF0000;
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RealTimeClock|= data&0xFFFF;
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//TODO: Clean the internal timer ?
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}
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return;
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case 8:
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rtc_EN=data&1;
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return;
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}
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}
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u32 ReadMem_aica_reg(u32 addr,u32 sz)
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{
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addr&=0x7FFF;
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if (sz==1)
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{
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if (addr==0x2C01)
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{
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return VREG;
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}
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else if (addr==0x2C00)
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{
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return ARMRST;
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}
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else
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{
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return libAICA_ReadReg(addr, sz);
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}
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}
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else
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{
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if (addr==0x2C00)
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{
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return (VREG<<8) | ARMRST;
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}
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else
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{
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return libAICA_ReadReg(addr, sz);
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}
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}
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}
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static void ArmSetRST()
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{
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ARMRST &= 1;
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arm_SetEnabled(ARMRST == 0);
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}
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void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
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{
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addr&=0x7FFF;
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if (sz==1)
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{
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if (addr==0x2C01)
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{
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VREG=data;
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INFO_LOG(AICA_ARM, "VREG = %02X", VREG);
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}
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else if (addr==0x2C00)
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{
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ARMRST=data;
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INFO_LOG(AICA_ARM, "ARMRST = %02X", ARMRST);
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ArmSetRST();
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}
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else
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{
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libAICA_WriteReg(addr,data,sz);
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}
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}
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else
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{
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if (addr==0x2C00)
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{
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VREG=(data>>8)&0xFF;
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ARMRST=data&0xFF;
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INFO_LOG(AICA_ARM, "VREG = %02X ARMRST %02X", VREG, ARMRST);
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ArmSetRST();
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}
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else
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{
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libAICA_WriteReg(addr,data,sz);
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}
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}
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}
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static int DreamcastSecond(int tag, int c, int j)
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{
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RealTimeClock++;
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prof_periodical();
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#if FEAT_SHREC != DYNAREC_NONE
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bm_Periodical_1s();
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#endif
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return SH4_MAIN_CLOCK;
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}
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//Init/res/term
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void aica_Init()
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{
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RealTimeClock = GetRTC_now();
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if (rtc_schid == -1)
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{
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rtc_schid = sh4_sched_register(0, &DreamcastSecond);
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sh4_sched_request(rtc_schid, SH4_MAIN_CLOCK);
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}
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}
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void aica_Reset(bool hard)
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{
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if (hard)
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aica_Init();
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VREG = 0;
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ARMRST = 0;
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}
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void aica_Term()
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{
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}
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static int dma_end_sched(int tag, int cycl, int jitt)
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{
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u32 len=SB_ADLEN & 0x7FFFFFFF;
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if (SB_ADLEN & 0x80000000)
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SB_ADEN = 0;
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else
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SB_ADEN = 1;
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SB_ADSTAR+=len;
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SB_ADSTAG+=len;
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SB_ADST = 0; // dma done
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SB_ADLEN = 0;
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// indicate that dma is not happening, or has been paused
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SB_ADSUSP |= 0x10;
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asic_RaiseInterrupt(holly_SPU_DMA);
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return 0;
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}
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static bool check_STAG(u32 addr)
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{
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#ifdef STRICT_MODE
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const u32 area = (addr >> 26) & 7;
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// Aica and G2 Ext dev #1 and #2 on area 0
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// G2 Ext dev #3 on area 5
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return area == 0 || area == 5;
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#else
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return true;
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#endif
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}
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static bool check_STAR(u32 addr)
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{
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#ifdef STRICT_MODE
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const u32 area = (addr >> 26) & 7;
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// System RAM and VRAM
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return area == 3 || area == 1;
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#else
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return true;
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#endif
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}
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static bool check_STAR_overrun(u32 addr)
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{
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#ifdef STRICT_MODE
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u32 bottom = (((SB_G2APRO >> 8) & 0x7f) << 20) | 0x08000000;
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u32 top = ((SB_G2APRO & 0x7f) << 20) | 0x080fffe0;
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return addr >= bottom && addr <= top;
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#else
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return true;
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#endif
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}
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template<u32 ENABLE, u32 START, u32 SRC, u32 DEST, u32 LEN, u32 DIR, HollyInterruptID interrupt, HollyInterruptID iainterrupt, HollyInterruptID ovinterrupt, const char *LogTag>
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void Write_DmaStart(u32 addr, u32 data)
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{
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u32& enableReg = SB_REGN_32(ENABLE);
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u32& startReg = SB_REGN_32(START);
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u32& sourceReg = SB_REGN_32(SRC);
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u32& destReg = SB_REGN_32(DEST);
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u32& lenReg = SB_REGN_32(LEN);
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const u32 dirReg = SB_REGN_32(DIR);
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if (!(data & 1) || !(enableReg & 1))
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return;
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u32 src = sourceReg;
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u32 dst = destReg;
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u32 len = lenReg & 0x7FFFFFFF;
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// STAR
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if (!check_STAR(src))
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{
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INFO_LOG(AICA, "%s: Invalid src address %08x", LogTag, src);
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startReg = 0;
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enableReg = 0;
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asic_RaiseInterrupt(iainterrupt);
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return;
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}
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// STAG
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if (!check_STAG(dst))
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{
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INFO_LOG(AICA, "%s: Invalid dst address %08x", LogTag, dst);
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startReg = 0;
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enableReg = 0;
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asic_RaiseInterrupt(iainterrupt);
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return;
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}
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// Overrun
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if (!check_STAR_overrun(src) || !check_STAR_overrun(src + len - 1))
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{
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INFO_LOG(AICA, "%s: Overrun address %08x len %x", LogTag, src, len);
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startReg = 0;
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enableReg = 0;
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asic_RaiseInterrupt(ovinterrupt);
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return;
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}
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if (dirReg == 1)
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{
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u32 t = src;
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src = dst;
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dst = t;
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DEBUG_LOG(AICA, "%s: DIR == 1 DMA Read to 0x%X from 0x%X %d bytes", LogTag, dst, src, len);
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}
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else
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DEBUG_LOG(AICA, "%s: DIR == 0 DMA Write to 0x%X from 0x%X %d bytes", LogTag, dst, src, len);
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WriteMemBlock_nommu_dma(dst, src, len);
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if (lenReg & 0x80000000)
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enableReg = 0;
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else
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enableReg = 1;
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sourceReg += len;
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destReg += len;
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startReg = 0; // dma done
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lenReg = 0;
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asic_RaiseInterrupt(interrupt);
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}
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static void Write_SB_ADST(u32 addr, u32 data)
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{
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//0x005F7800 SB_ADSTAG RW AICA:G2-DMA G2 start address
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//0x005F7804 SB_ADSTAR RW AICA:G2-DMA system memory start address
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//0x005F7808 SB_ADLEN RW AICA:G2-DMA length
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//0x005F780C SB_ADDIR RW AICA:G2-DMA direction
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//0x005F7810 SB_ADTSEL RW AICA:G2-DMA trigger select
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//0x005F7814 SB_ADEN RW AICA:G2-DMA enable
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//0x005F7818 SB_ADST RW AICA:G2-DMA start
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//0x005F781C SB_ADSUSP RW AICA:G2-DMA suspend
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if (data&1)
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{
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if (SB_ADEN&1)
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{
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u32 src = SB_ADSTAR;
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u32 dst = SB_ADSTAG;
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u32 len = SB_ADLEN & 0x7FFFFFFF;
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if (!check_STAR(src))
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{
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INFO_LOG(AICA, "AICA-DMA : Invalid src address %08x", src);
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SB_ADST = 0;
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SB_ADEN = 0;
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asic_RaiseInterrupt(holly_AICA_ILLADDR);
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return;
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}
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if (!check_STAG(dst))
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{
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INFO_LOG(AICA, "AICA-DMA : Invalid dst address %08x", dst);
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SB_ADST = 0;
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SB_ADEN = 0;
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asic_RaiseInterrupt(holly_AICA_ILLADDR);
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return;
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}
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// Overrun
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if (!check_STAR_overrun(src) || !check_STAR_overrun(src + len - 1))
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{
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INFO_LOG(AICA, "AICA-DMA : Overrun address %08x len %x", src, len);
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SB_ADST = 0;
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SB_ADEN = 0;
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asic_RaiseInterrupt(holly_AICA_OVERRUN);
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return;
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}
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if ((SB_ADDIR&1)==1)
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{
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//swap direction
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u32 tmp=src;
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src=dst;
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dst=tmp;
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DEBUG_LOG(AICA, "AICA-DMA : SB_ADDIR==1 DMA Read to 0x%X from 0x%X %x bytes", dst, src, SB_ADLEN);
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}
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else
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DEBUG_LOG(AICA, "AICA-DMA : SB_ADDIR==0:DMA Write to 0x%X from 0x%X %x bytes", dst, src, SB_ADLEN);
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WriteMemBlock_nommu_dma(dst,src,len);
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// indicate that dma is in progress
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SB_ADST = 1;
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SB_ADSUSP &= ~0x10;
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// Schedule the end of DMA transfer interrupt
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int cycles = len * (SH4_MAIN_CLOCK / 2 / 25000000); // 16 bits @ 25 MHz
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if (cycles < 4096)
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dma_end_sched(0, 0, 0);
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else
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sh4_sched_request(dma_sched_id, cycles);
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}
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}
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}
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template<u32 STAG, HollyInterruptID iainterrupt, const char *LogTag>
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void Write_SB_STAG(u32 addr, u32 data)
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{
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u32& stagReg = sb_regs[(STAG - SB_BASE) / 4].data32;
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stagReg = data & 0x1FFFFFE0;
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if (!check_STAG(data))
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{
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INFO_LOG(AICA, "%s Write_SB_STAG: Invalid address %08x", LogTag, data);
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asic_RaiseInterrupt(iainterrupt);
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}
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}
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template<u32 STAR, HollyInterruptID iainterrupt, const char *LogTag>
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void Write_SB_STAR(u32 addr, u32 data)
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{
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u32& starReg = sb_regs[(STAR - SB_BASE) / 4].data32;
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starReg = data & 0x1FFFFFE0;
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if (!check_STAR(data))
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{
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INFO_LOG(AICA, "%s Write_SB_STAR: Invalid address %08x", LogTag, data);
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asic_RaiseInterrupt(iainterrupt);
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}
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}
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void Write_SB_G2APRO(u32 addr, u32 data)
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{
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if ((data >> 16) == 0x4659)
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SB_G2APRO = data & 0x00007f7f;
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}
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extern const char AICA_TAG[] = "G2-AICA DMA";
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extern const char EXT1_TAG[] = "G2-EXT1 DMA";
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extern const char EXT2_TAG[] = "G2-EXT2 DMA";
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extern const char DDEV_TAG[] = "G2-DDev DMA";
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void aica_sb_Init()
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{
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// G2-DMA registers
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// AICA
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sb_rio_register(SB_ADST_addr, RIO_WF, nullptr, &Write_SB_ADST);
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#ifdef STRICT_MODE
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sb_rio_register(SB_ADSTAR_addr, RIO_WF, nullptr, &Write_SB_STAR<SB_ADSTAR_addr, holly_AICA_ILLADDR, AICA_TAG>);
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sb_rio_register(SB_ADSTAG_addr, RIO_WF, nullptr, &Write_SB_STAG<SB_ADSTAG_addr, holly_AICA_ILLADDR, AICA_TAG>);
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#endif
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// G2 Ext device #1
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sb_rio_register(SB_E1ST_addr, RIO_WF, nullptr, &Write_DmaStart<SB_E1EN_addr, SB_E1ST_addr, SB_E1STAR_addr, SB_E1STAG_addr, SB_E1LEN_addr,
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SB_E1DIR_addr, holly_EXT_DMA1, holly_EXT1_ILLADDR, holly_EXT1_OVERRUN, EXT1_TAG>);
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sb_rio_register(SB_E1STAR_addr, RIO_WF, nullptr, &Write_SB_STAR<SB_E1STAR_addr, holly_EXT1_ILLADDR, EXT1_TAG>);
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sb_rio_register(SB_E1STAG_addr, RIO_WF, nullptr, &Write_SB_STAG<SB_E1STAG_addr, holly_EXT1_ILLADDR, EXT1_TAG>);
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// G2 Ext device #2
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sb_rio_register(SB_E2ST_addr, RIO_WF, nullptr, &Write_DmaStart<SB_E2EN_addr, SB_E2ST_addr, SB_E2STAR_addr, SB_E2STAG_addr, SB_E2LEN_addr,
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SB_E2DIR_addr, holly_EXT_DMA2, holly_EXT2_ILLADDR, holly_EXT2_OVERRUN, EXT2_TAG>);
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sb_rio_register(SB_E2STAR_addr, RIO_WF, nullptr, &Write_SB_STAR<SB_E2STAR_addr, holly_EXT2_ILLADDR, EXT2_TAG>);
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sb_rio_register(SB_E2STAG_addr, RIO_WF, nullptr, &Write_SB_STAG<SB_E2STAG_addr, holly_EXT2_ILLADDR, EXT2_TAG>);
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// G2 Ext device #3
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sb_rio_register(SB_DDST_addr, RIO_WF, nullptr, &Write_DmaStart<SB_DDEN_addr, SB_DDST_addr, SB_DDSTAR_addr, SB_DDSTAG_addr, SB_DDLEN_addr,
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SB_DDDIR_addr, holly_DEV_DMA, holly_DEV_ILLADDR, holly_DEV_OVERRUN, DDEV_TAG>);
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sb_rio_register(SB_DDSTAR_addr, RIO_WF, nullptr, &Write_SB_STAR<SB_DDSTAR_addr, holly_DEV_ILLADDR, DDEV_TAG>);
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sb_rio_register(SB_DDSTAG_addr, RIO_WF, nullptr, &Write_SB_STAG<SB_DDSTAG_addr, holly_DEV_ILLADDR, DDEV_TAG>);
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sb_rio_register(SB_G2APRO_addr, RIO_WO_FUNC, nullptr, &Write_SB_G2APRO);
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dma_sched_id = sh4_sched_register(0, &dma_end_sched);
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}
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void aica_sb_Reset(bool hard)
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{
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}
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void aica_sb_Term()
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{
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}
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