597 lines
14 KiB
C++
597 lines
14 KiB
C++
#include "mmu.h"
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#include "hw/mem/addrspace.h"
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#include "hw/sh4/sh4_if.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_core.h"
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#include "debug/gdb_server.h"
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#include "serialize.h"
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TLB_Entry UTLB[64];
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TLB_Entry ITLB[4];
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static u32 ITLB_LRU_USE[64];
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bool mmuOn;
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//SQ fast remap , mainly hackish , assumes 1MB pages
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//max 64MB can be remapped on SQ
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// Used when FullMMU is off
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u32 sq_remap[64];
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/*
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MMU support code
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This is mostly hacked-on as the core was never meant to have mmu support
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There are two modes, one with 'full' mmu emulation (for wince/bleem/wtfever)
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and a fast-hack mode for 1mb sqremaps (for katana)
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*/
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#ifndef FAST_MMU
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#include "ccn.h"
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#endif
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#include "hw/sh4/sh4_mem.h"
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//#define TRACE_WINCE_SYSCALLS
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#ifdef TRACE_WINCE_SYSCALLS
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#include "wince.h"
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u32 unresolved_ascii_string;
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u32 unresolved_unicode_string;
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#endif
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#define printf_mmu(...) DEBUG_LOG(SH4, __VA_ARGS__)
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constexpr u32 ITLB_LRU_OR[4] =
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{
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0x00,//000xxx
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0x20,//1xx00x
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0x14,//x1x1x0
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0x0B,//xx1x11
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};
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constexpr u32 ITLB_LRU_AND[4] =
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{
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0x07,//000xxx
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0x39,//1xx00x
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0x3E,//x1x1x0
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0x3F,//xx1x11
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};
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#ifndef FAST_MMU
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync
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bool UTLB_Sync(u32 entry)
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{
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printf_mmu("UTLB MEM remap %d : 0x%X to 0x%X : %d asid %d size %d", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10, UTLB[entry].Data.V,
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UTLB[entry].Address.ASID, UTLB[entry].Data.SZ0 + UTLB[entry].Data.SZ1 * 2);
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if (UTLB[entry].Data.V == 0)
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return true;
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if ((UTLB[entry].Address.VPN & (0xFC000000 >> 10)) == (0xE0000000 >> 10))
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{
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// Used when FullMMU is off
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u32 vpn_sq = ((UTLB[entry].Address.VPN & 0x7FFFF) >> 10) & 0x3F;//upper bits are always known [0xE0/E1/E2/E3]
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sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10;
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return true;
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}
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else
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{
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return false;
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}
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}
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//sync mem mapping to mmu , suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync
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void ITLB_Sync(u32 entry)
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{
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printf_mmu("ITLB MEM remap %d : 0x%X to 0x%X : %d", entry, ITLB[entry].Address.VPN << 10, ITLB[entry].Data.PPN << 10, ITLB[entry].Data.V);
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}
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#endif
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template<typename F>
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static void mmuException(MmuError mmu_error, u32 address, u32 am, F raise)
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{
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printf_mmu("MMU exception -> pc = 0x%X : ", Sh4cntx.pc);
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CCN_TEA = address;
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CCN_PTEH.VPN = address >> 10;
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switch (mmu_error)
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{
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case MmuError::NONE:
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die("Error: mmu_error == MmuError::NONE)");
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return;
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case MmuError::TLB_MISS:
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printf_mmu("MmuError::UTLB_MISS 0x%X, handled", address);
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if (am == MMU_TT_DWRITE)
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raise(Sh4Ex_TlbMissWrite);
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else
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raise(Sh4Ex_TlbMissRead);
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return;
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case MmuError::TLB_MHIT:
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ERROR_LOG(SH4, "MmuError::TLB_MHIT @ 0x%X", address);
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raise(Sh4Ex_TlbMultiHit);
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break;
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//Mem is read/write protected (depends on translation type)
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case MmuError::PROTECTED:
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printf_mmu("MmuError::PROTECTED 0x%X, handled", address);
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if (am == MMU_TT_DWRITE)
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raise(Sh4Ex_TlbProtViolWrite);
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else
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raise(Sh4Ex_TlbProtViolRead);
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return;
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//Mem is write protected , firstwrite
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case MmuError::FIRSTWRITE:
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printf_mmu("MmuError::FIRSTWRITE");
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verify(am == MMU_TT_DWRITE);
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raise(Sh4Ex_TlbInitPageWrite);
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return;
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//data read/write misaligned
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case MmuError::BADADDR:
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if (am == MMU_TT_DWRITE) //WADDERR - Write Data Address Error
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{
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printf_mmu("MmuError::BADADDR(dw) 0x%X", address);
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raise(Sh4Ex_AddressErrorWrite);
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}
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else if (am == MMU_TT_DREAD) //RADDERR - Read Data Address Error
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{
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printf_mmu("MmuError::BADADDR(dr) 0x%X", address);
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raise(Sh4Ex_AddressErrorRead);
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}
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else //IADDERR - Instruction Address Error
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{
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#ifdef TRACE_WINCE_SYSCALLS
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if (!print_wince_syscall(address))
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#endif
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printf_mmu("MmuError::BADADDR(i) 0x%X", address);
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raise(Sh4Ex_AddressErrorRead);
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}
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return;
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default:
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die("Unknown mmu_error");
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}
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}
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[[noreturn]] void mmu_raise_exception(MmuError mmu_error, u32 address, u32 am)
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{
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mmuException(mmu_error, address, am, [](Sh4ExceptionCode event) {
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debugger::debugTrap(event); // FIXME CCN_TEA and CCN_PTEH have been updated already
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throw SH4ThrownException(Sh4cntx.pc - 2, event);
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});
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die("Unknown mmu_error");
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}
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void DoMMUException(u32 address, MmuError mmu_error, u32 access_type)
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{
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mmuException(mmu_error, address, access_type, [](Sh4ExceptionCode event) {
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Do_Exception(Sh4cntx.pc, event);
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});
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}
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bool mmu_match(u32 va, CCN_PTEH_type Address, CCN_PTEL_type Data)
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{
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if (Data.V == 0)
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return false;
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u32 sz = Data.SZ1 * 2 + Data.SZ0;
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u32 mask = mmu_mask[sz];
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if ((((Address.VPN << 10) & mask) == (va & mask)))
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{
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bool needAsidMatch = Data.SH == 0 && (Sh4cntx.sr.MD == 0 || CCN_MMUCR.SV == 0);
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if (!needAsidMatch || Address.ASID == CCN_PTEH.ASID)
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return true;
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}
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return false;
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}
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#ifndef FAST_MMU
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//Do a full lookup on the UTLB entry's
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MmuError mmu_full_lookup(u32 va, const TLB_Entry** tlb_entry_ret, u32& rv)
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{
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CCN_MMUCR.URC++;
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if (CCN_MMUCR.URB == CCN_MMUCR.URC)
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CCN_MMUCR.URC = 0;
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*tlb_entry_ret = nullptr;
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for (const TLB_Entry& tlb_entry : UTLB)
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{
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if (mmu_match(va, tlb_entry.Address, tlb_entry.Data))
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{
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if (*tlb_entry_ret != nullptr)
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return MmuError::TLB_MHIT;
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*tlb_entry_ret = &tlb_entry;
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u32 sz = tlb_entry.Data.SZ1 * 2 + tlb_entry.Data.SZ0;
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u32 mask = mmu_mask[sz];
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//VPN->PPN | low bits
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rv = ((tlb_entry.Data.PPN << 10) & mask) | (va & ~mask);
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}
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}
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if (*tlb_entry_ret == nullptr)
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return MmuError::TLB_MISS;
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else
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return MmuError::NONE;
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}
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//Simple QACR translation for mmu (when AT is off)
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static u32 mmu_QACR_SQ(u32 va)
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{
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int sqi = (va >> 5) & 1;
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u32 addr = (sqi ? CCN_QACR1.Area : CCN_QACR0.Area) << 26;
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addr |= va & 0x03ffffe0;
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return addr;
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}
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template<u32 translation_type>
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MmuError mmu_full_SQ(u32 va, u32& rv)
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{
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if ((va & 3) || (CCN_MMUCR.SQMD == 1 && Sh4cntx.sr.MD == 0))
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//here, or after ?
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return MmuError::BADADDR;
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if (CCN_MMUCR.AT)
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{
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//Address=Dest&0xFFFFFFE0;
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const TLB_Entry *entry;
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MmuError lookup = mmu_full_lookup(va, &entry, rv);
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rv &= ~31;//lower 5 bits are forced to 0
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if (lookup != MmuError::NONE)
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return lookup;
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u32 md = entry->Data.PR >> 1;
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//Priv mode protection
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if (md == 0 && Sh4cntx.sr.MD == 0)
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return MmuError::PROTECTED;
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//Write Protection (Lock or FW)
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((entry->Data.PR & 1) == 0)
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return MmuError::PROTECTED;
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else if (entry->Data.D == 0)
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return MmuError::FIRSTWRITE;
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}
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}
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else
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{
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rv = mmu_QACR_SQ(va);
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}
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return MmuError::NONE;
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}
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template MmuError mmu_full_SQ<MMU_TT_DREAD>(u32 va, u32& rv);
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template MmuError mmu_full_SQ<MMU_TT_DWRITE>(u32 va, u32& rv);
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template<u32 translation_type>
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MmuError mmu_data_translation(u32 va, u32& rv)
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{
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((va & 0xFC000000) == 0xE0000000)
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{
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MmuError lookup = mmu_full_SQ<MMU_TT_DWRITE>(va, rv);
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if (lookup != MmuError::NONE)
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return lookup;
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rv = va; //SQ writes are not translated, only write backs are.
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return MmuError::NONE;
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}
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}
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if (Sh4cntx.sr.MD == 0 && (va & 0x80000000) != 0)
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//if on kernel, and not SQ addr -> error
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return MmuError::BADADDR;
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if ((va & 0xFC000000) == 0x7C000000)
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{
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// 7C000000 to 7FFFFFFF in P0/U0 not translated
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rv = va;
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return MmuError::NONE;
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}
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if (fast_reg_lut[va >> 29] != 0)
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{
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// P1, P2 and P4 aren't translated
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rv = va;
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return MmuError::NONE;
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}
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const TLB_Entry *entry;
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MmuError lookup = mmu_full_lookup(va, &entry, rv);
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if (lookup != MmuError::NONE)
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return lookup;
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#ifdef TRACE_WINCE_SYSCALLS
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if (unresolved_unicode_string != 0)
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{
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if (va == unresolved_unicode_string)
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{
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unresolved_unicode_string = 0;
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INFO_LOG(SH4, "RESOLVED %s", get_unicode_string(va).c_str());
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}
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}
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#endif
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u32 md = entry->Data.PR >> 1;
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//0X & User mode-> protection violation
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//Priv mode protection
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if (md == 0 && Sh4cntx.sr.MD == 0)
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return MmuError::PROTECTED;
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//X0 -> read olny
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//X1 -> read/write , can be FW
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//Write Protection (Lock or FW)
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if (translation_type == MMU_TT_DWRITE)
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{
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if ((entry->Data.PR & 1) == 0)
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return MmuError::PROTECTED;
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else if (entry->Data.D == 0)
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return MmuError::FIRSTWRITE;
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}
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if ((rv & 0x1C000000) == 0x1C000000)
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// map 1C000000-1FFFFFFF to P4 memory-mapped registers
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rv |= 0xF0000000;
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return MmuError::NONE;
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}
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template MmuError mmu_data_translation<MMU_TT_DREAD>(u32 va, u32& rv);
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template MmuError mmu_data_translation<MMU_TT_DWRITE>(u32 va, u32& rv);
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MmuError mmu_instruction_translation(u32 va, u32& rv)
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{
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if (Sh4cntx.sr.MD == 0 && (va & 0x80000000) != 0)
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// User mode on kernel address
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return MmuError::BADADDR;
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if ((va >> 29) == 7)
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// P4 not executable
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return MmuError::BADADDR;
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if (fast_reg_lut[va >> 29] != 0)
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{
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// P1 and P2 aren't translated
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rv = va;
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return MmuError::NONE;
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}
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const TLB_Entry *entry;
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MmuError lookup = mmu_instruction_lookup(va, &entry, rv);
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if (lookup != MmuError::NONE)
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return lookup;
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u32 md = entry->Data.PR >> 1;
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//0X & User mode-> protection violation
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//Priv mode protection
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if (md == 0 && Sh4cntx.sr.MD == 0)
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return MmuError::PROTECTED;
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return MmuError::NONE;
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}
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#endif
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MmuError mmu_instruction_lookup(u32 va, const TLB_Entry** tlb_entry_ret, u32& rv)
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{
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bool mmach = false;
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retry_ITLB_Match:
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*tlb_entry_ret = nullptr;
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for (const TLB_Entry& entry : ITLB)
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{
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if (entry.Data.V == 0)
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continue;
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u32 sz = entry.Data.SZ1 * 2 + entry.Data.SZ0;
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u32 mask = mmu_mask[sz];
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if ((((entry.Address.VPN << 10) & mask) == (va & mask)))
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{
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bool needAsidMatch = entry.Data.SH == 0 && (Sh4cntx.sr.MD == 0 || CCN_MMUCR.SV == 0);
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if (!needAsidMatch || entry.Address.ASID == CCN_PTEH.ASID)
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{
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if (*tlb_entry_ret != nullptr)
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return MmuError::TLB_MHIT;
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*tlb_entry_ret = &entry;
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//VPN->PPN | low bits
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rv = ((entry.Data.PPN << 10) & mask) | (va & ~mask);
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}
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}
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}
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if (*tlb_entry_ret == nullptr)
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{
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#ifndef FAST_MMU
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verify(!mmach);
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#else
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// the matching may be approximative
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if (mmach)
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return MmuError::TLB_MISS;
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#endif
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const TLB_Entry *tlb_entry;
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MmuError lookup = mmu_full_lookup(va, &tlb_entry, rv);
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if (lookup != MmuError::NONE)
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return lookup;
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u32 replace_index = ITLB_LRU_USE[CCN_MMUCR.LRUI];
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verify(replace_index != 0xFFFFFFFF);
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ITLB[replace_index] = *tlb_entry;
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ITLB_Sync(replace_index);
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mmach = true;
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goto retry_ITLB_Match;
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}
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CCN_MMUCR.LRUI &= ITLB_LRU_AND[*tlb_entry_ret - ITLB];
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CCN_MMUCR.LRUI |= ITLB_LRU_OR[*tlb_entry_ret - ITLB];
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return MmuError::NONE;
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}
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void mmu_set_state()
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{
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if (CCN_MMUCR.AT == 1)
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{
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// Detect if we're running Windows CE
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static const char magic[] = { 'S', 0, 'H', 0, '-', 0, '4', 0, ' ', 0, 'K', 0, 'e', 0, 'r', 0, 'n', 0, 'e', 0, 'l', 0 };
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if (memcmp(GetMemPtr(0x8c0110a8, 4), magic, sizeof(magic)) == 0
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|| memcmp(GetMemPtr(0x8c011118, 4), magic, sizeof(magic)) == 0)
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{
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mmuOn = true;
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NOTICE_LOG(SH4, "Enabling Full MMU support");
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}
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}
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else
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{
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mmuOn = false;
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}
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SetMemoryHandlers();
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setSqwHandler();
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}
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#ifdef FAST_MMU
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u32 mmuAddressLUT[0x100000];
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#endif
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void MMU_init()
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{
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memset(ITLB_LRU_USE, 0xFF, sizeof(ITLB_LRU_USE));
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for (u32 e = 0; e<4; e++)
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{
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u32 match_key = ((~ITLB_LRU_AND[e]) & 0x3F);
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u32 match_mask = match_key | ITLB_LRU_OR[e];
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for (u32 i = 0; i < std::size(ITLB_LRU_USE); i++)
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{
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if ((i & match_mask) == match_key)
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{
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verify(ITLB_LRU_USE[i] == 0xFFFFFFFF);
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ITLB_LRU_USE[i] = e;
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}
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}
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}
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mmu_set_state();
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#ifdef FAST_MMU
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// pre-fill kernel memory
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for (u32 vpn = std::size(mmuAddressLUT) / 2; vpn < std::size(mmuAddressLUT); vpn++)
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mmuAddressLUT[vpn] = vpn << 12;
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#endif
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}
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void MMU_reset()
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{
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memset(UTLB, 0, sizeof(UTLB));
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memset(ITLB, 0, sizeof(ITLB));
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mmu_set_state();
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mmu_flush_table();
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memset(sq_remap, 0, sizeof(sq_remap));
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}
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void MMU_term()
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{
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}
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#ifndef FAST_MMU
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void mmu_flush_table()
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{
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for (TLB_Entry& entry : ITLB)
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entry.Data.V = 0;
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for (TLB_Entry& entry : UTLB)
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entry.Data.V = 0;
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}
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#endif
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template<typename T>
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T DYNACALL mmu_ReadMem(u32 adr)
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{
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if (adr & (std::min((int)sizeof(T), 4) - 1))
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// Unaligned
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mmu_raise_exception(MmuError::BADADDR, adr, MMU_TT_DREAD);
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u32 addr;
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MmuError rv = mmu_data_translation<MMU_TT_DREAD>(adr, addr);
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if (rv != MmuError::NONE)
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mmu_raise_exception(rv, adr, MMU_TT_DREAD);
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return addrspace::readt<T>(addr);
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}
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template u8 mmu_ReadMem(u32 adr);
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template u16 mmu_ReadMem(u32 adr);
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template u32 mmu_ReadMem(u32 adr);
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template u64 mmu_ReadMem(u32 adr);
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u16 DYNACALL mmu_IReadMem16(u32 vaddr)
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{
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if (vaddr & (sizeof(u16) - 1))
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// Unaligned
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mmu_raise_exception(MmuError::BADADDR, vaddr, MMU_TT_IREAD);
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u32 addr;
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MmuError rv = mmu_instruction_translation(vaddr, addr);
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if (rv != MmuError::NONE)
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mmu_raise_exception(rv, vaddr, MMU_TT_IREAD);
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return addrspace::read16(addr);
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}
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template<typename T>
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void DYNACALL mmu_WriteMem(u32 adr, T data)
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{
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if (adr & (std::min((int)sizeof(T), 4) - 1))
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// Unaligned
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mmu_raise_exception(MmuError::BADADDR, adr, MMU_TT_DWRITE);
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u32 addr;
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MmuError rv = mmu_data_translation<MMU_TT_DWRITE>(adr, addr);
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if (rv != MmuError::NONE)
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mmu_raise_exception(rv, adr, MMU_TT_DWRITE);
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addrspace::writet<T>(addr, data);
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}
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template void mmu_WriteMem(u32 adr, u8 data);
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template void mmu_WriteMem(u32 adr, u16 data);
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template void mmu_WriteMem(u32 adr, u32 data);
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template void mmu_WriteMem(u32 adr, u64 data);
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void mmu_TranslateSQW(u32 adr, u32 *out)
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{
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if (!mmuOn)
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{
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//This will only work for 1 mb pages .. hopefully nothing else is used
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//*FIXME* to work for all page sizes ?
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*out = sq_remap[(adr >> 20) & 0x3F] | (adr & 0xFFFE0);
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}
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else
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{
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u32 addr;
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MmuError tv = mmu_full_SQ<MMU_TT_DREAD>(adr, addr);
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if (tv != MmuError::NONE)
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mmu_raise_exception(tv, adr, MMU_TT_DREAD);
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*out = addr;
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}
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}
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void mmu_serialize(Serializer& ser)
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{
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ser << UTLB;
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ser << ITLB;
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ser << sq_remap;
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}
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void mmu_deserialize(Deserializer& deser)
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{
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deser.skip(8, Deserializer::V33); // CCN_QACR_TR
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deser >> UTLB;
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deser >> ITLB;
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deser >> sq_remap;
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deser.skip(64 * 4, Deserializer::V23); // ITLB_LRU_USE
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}
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