sh4: non-functional changes
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Flyinghead
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305ab38ac8
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cffb272abd
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@ -76,17 +76,17 @@ void UpdateTMU_i(u32 Cycles)
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u32 tmu_ch_base[3];
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u64 tmu_ch_base64[3];
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u32 read_TMU_TCNTch(u32 ch)
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static u32 read_TMU_TCNTch(u32 ch)
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{
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return tmu_ch_base[ch] - ((sh4_sched_now64() >> tmu_shift[ch])&tmu_mask[ch]);
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}
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s64 read_TMU_TCNTch64(u32 ch)
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static s64 read_TMU_TCNTch64(u32 ch)
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{
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return tmu_ch_base64[ch] - ((sh4_sched_now64() >> tmu_shift[ch])&tmu_mask64[ch]);
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}
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void sched_chan_tick(int ch)
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static void sched_chan_tick(int ch)
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{
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//schedule next interrupt
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//return TMU_TCOR(ch) << tmu_shift[ch];
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@ -105,10 +105,9 @@ void sched_chan_tick(int ch)
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sh4_sched_request(tmu_sched[ch], cycles );
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else
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sh4_sched_request(tmu_sched[ch], -1);
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//sched_tmu_cb
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}
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void write_TMU_TCNTch(u32 ch, u32 data)
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static void write_TMU_TCNTch(u32 ch, u32 data)
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{
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//u32 TCNT=read_TMU_TCNTch(ch);
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tmu_ch_base[ch]=data+((sh4_sched_now64()>>tmu_shift[ch])&tmu_mask[ch]);
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@ -129,7 +128,7 @@ void write_TMU_TCNT(u32 addr, u32 data)
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write_TMU_TCNTch(ch,data);
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}
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void turn_on_off_ch(u32 ch, bool on)
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static void turn_on_off_ch(u32 ch, bool on)
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{
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u32 TCNT=read_TMU_TCNTch(ch);
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tmu_mask[ch]=on?0xFFFFFFFF:0x00000000;
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@ -138,7 +137,7 @@ void turn_on_off_ch(u32 ch, bool on)
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}
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//Update internal counter registers
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void UpdateTMUCounts(u32 reg)
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static void UpdateTMUCounts(u32 reg)
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{
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InterruptPend(tmu_intID[reg],TMU_TCR(reg) & tmu_underflow);
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InterruptMask(tmu_intID[reg],TMU_TCR(reg) & tmu_UNIE);
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@ -196,18 +195,18 @@ void TMU_TCR_write(u32 addr, u32 data)
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}
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//Chan 2 not used functions
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u32 TMU_TCPR2_read(u32 addr)
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static u32 TMU_TCPR2_read(u32 addr)
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{
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INFO_LOG(SH4, "Read from TMU_TCPR2 - this register should be not used on Dreamcast according to docs");
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return 0;
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}
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void TMU_TCPR2_write(u32 addr, u32 data)
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static void TMU_TCPR2_write(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "Write to TMU_TCPR2 - this register should be not used on Dreamcast according to docs, data=%d", data);
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}
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void write_TMU_TSTR(u32 addr, u32 data)
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static void write_TMU_TSTR(u32 addr, u32 data)
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{
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TMU_TSTR=data;
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//?
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@ -216,7 +215,7 @@ void write_TMU_TSTR(u32 addr, u32 data)
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turn_on_off_ch(i,data&(1<<i));
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}
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int sched_tmu_cb(int ch, int sch_cycl, int jitter)
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static int sched_tmu_cb(int ch, int sch_cycl, int jitter)
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{
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if (tmu_mask[ch]) {
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@ -95,7 +95,6 @@ static INLINE void SetXD(u32 n,f64 val)
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xf[(n<<1) | 0]=t.sgl[1];
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}
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bool Do_Interrupt(u32 intEvn);
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bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect);
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struct SH4ThrownException {
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@ -13,24 +13,12 @@ u8* sh4_dyna_rcb;
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static INLINE void ChangeGPR()
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{
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u32 temp;
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for (int i=0;i<8;i++)
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{
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temp=r[i];
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r[i]=r_bank[i];
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r_bank[i]=temp;
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}
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std::swap((u32 (&)[8])r, r_bank);
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}
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static INLINE void ChangeFP()
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{
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u32 temp;
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for (int i=0;i<16;i++)
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{
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temp=fr_hex[i];
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fr_hex[i]=xf_hex[i];
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xf_hex[i]=temp;
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}
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std::swap((f32 (&)[16])Sh4cntx.xffr, *(f32 (*)[16])&Sh4cntx.xffr[16]);
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}
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//called when sr is changed and we must check for reg banks etc.
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@ -38,8 +38,57 @@ struct InterptSourceList_Entry
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u32 GetPrLvl() const { return ((*PrioReg)>>Shift)&0xF; }
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};
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//Can't be statically initialised because registers are dynamically allocated
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InterptSourceList_Entry InterruptSourceList[28];
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static const InterptSourceList_Entry InterruptSourceList[28] =
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{
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//IRL
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{IRLP9,0x320},//sh4_IRL_9 = KMIID(sh4_int,0x320,0),
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{IRLP11,0x360},//sh4_IRL_11 = KMIID(sh4_int,0x360,1),
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{IRLP13,0x3A0},//sh4_IRL_13 = KMIID(sh4_int,0x3A0,2),
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//HUDI
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{GIPC(0),0x600},//sh4_HUDI_HUDI = KMIID(sh4_int,0x600,3), /* H-UDI underflow */
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//GPIO (missing on dc ?)
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{GIPC(3),0x620},//sh4_GPIO_GPIOI = KMIID(sh4_int,0x620,4),
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//DMAC
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{GIPC(2),0x640},//sh4_DMAC_DMTE0 = KMIID(sh4_int,0x640,5),
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{GIPC(2),0x660},//sh4_DMAC_DMTE1 = KMIID(sh4_int,0x660,6),
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{GIPC(2),0x680},//sh4_DMAC_DMTE2 = KMIID(sh4_int,0x680,7),
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{GIPC(2),0x6A0},//sh4_DMAC_DMTE3 = KMIID(sh4_int,0x6A0,8),
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{GIPC(2),0x6C0},//sh4_DMAC_DMAE = KMIID(sh4_int,0x6C0,9),
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//TMU
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{GIPA(3),0x400},//sh4_TMU0_TUNI0 = KMIID(sh4_int,0x400,10), /* TMU0 underflow */
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{GIPA(2),0x420},//sh4_TMU1_TUNI1 = KMIID(sh4_int,0x420,11), /* TMU1 underflow */
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{GIPA(1),0x440},//sh4_TMU2_TUNI2 = KMIID(sh4_int,0x440,12), /* TMU2 underflow */
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{GIPA(1),0x460},//sh4_TMU2_TICPI2 = KMIID(sh4_int,0x460,13),
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//RTC
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{GIPA(0),0x480},//sh4_RTC_ATI = KMIID(sh4_int,0x480,14),
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{GIPA(0),0x4A0},//sh4_RTC_PRI = KMIID(sh4_int,0x4A0,15),
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{GIPA(0),0x4C0},//sh4_RTC_CUI = KMIID(sh4_int,0x4C0,16),
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//SCI
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{GIPB(1),0x4E0},//sh4_SCI1_ERI = KMIID(sh4_int,0x4E0,17),
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{GIPB(1),0x500},//sh4_SCI1_RXI = KMIID(sh4_int,0x500,18),
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{GIPB(1),0x520},//sh4_SCI1_TXI = KMIID(sh4_int,0x520,19),
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{GIPB(1),0x540},//sh4_SCI1_TEI = KMIID(sh4_int,0x540,29),
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//SCIF
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{GIPC(1),0x700},//sh4_SCIF_ERI = KMIID(sh4_int,0x700,21),
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{GIPC(1),0x720},//sh4_SCIF_RXI = KMIID(sh4_int,0x720,22),
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{GIPC(1),0x740},//sh4_SCIF_BRI = KMIID(sh4_int,0x740,23),
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{GIPC(1),0x760},//sh4_SCIF_TXI = KMIID(sh4_int,0x760,24),
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//WDT
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{GIPB(3),0x560},//sh4_WDT_ITI = KMIID(sh4_int,0x560,25),
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//REF
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{GIPB(2),0x580},//sh4_REF_RCMI = KMIID(sh4_int,0x580,26),
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{GIPA(2),0x5A0},//sh4_REF_ROVI = KMIID(sh4_int,0x5A0,27),
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};
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//Maps siid -> EventID
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alignas(64) u16 InterruptEnvId[32] = { 0 };
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@ -48,8 +97,7 @@ alignas(64) u32 InterruptBit[32] = { 0 };
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//Maps sh4 interrupt level to inclusive bitfield
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alignas(64) u32 InterruptLevelBit[16] = { 0 };
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bool Do_Interrupt(u32 intEvn);
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bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect);
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static bool Do_Interrupt(u32 intEvn);
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u32 interrupt_vpend; // Vector of pending interrupts
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u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts)
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@ -142,7 +190,7 @@ void ResetInterruptMask(InterruptID intr)
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}
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bool Do_Interrupt(u32 intEvn)
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static bool Do_Interrupt(u32 intEvn)
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{
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CCN_INTEVT = intEvn;
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@ -181,60 +229,6 @@ bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect)
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//Init/Res/Term
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void interrupts_init()
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{
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InterptSourceList_Entry InterruptSourceList2[]=
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{
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//IRL
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{IRLP9,0x320},//sh4_IRL_9 = KMIID(sh4_int,0x320,0),
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{IRLP11,0x360},//sh4_IRL_11 = KMIID(sh4_int,0x360,1),
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{IRLP13,0x3A0},//sh4_IRL_13 = KMIID(sh4_int,0x3A0,2),
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//HUDI
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{GIPC(0),0x600},//sh4_HUDI_HUDI = KMIID(sh4_int,0x600,3), /* H-UDI underflow */
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//GPIO (missing on dc ?)
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{GIPC(3),0x620},//sh4_GPIO_GPIOI = KMIID(sh4_int,0x620,4),
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//DMAC
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{GIPC(2),0x640},//sh4_DMAC_DMTE0 = KMIID(sh4_int,0x640,5),
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{GIPC(2),0x660},//sh4_DMAC_DMTE1 = KMIID(sh4_int,0x660,6),
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{GIPC(2),0x680},//sh4_DMAC_DMTE2 = KMIID(sh4_int,0x680,7),
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{GIPC(2),0x6A0},//sh4_DMAC_DMTE3 = KMIID(sh4_int,0x6A0,8),
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{GIPC(2),0x6C0},//sh4_DMAC_DMAE = KMIID(sh4_int,0x6C0,9),
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//TMU
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{GIPA(3),0x400},//sh4_TMU0_TUNI0 = KMIID(sh4_int,0x400,10), /* TMU0 underflow */
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{GIPA(2),0x420},//sh4_TMU1_TUNI1 = KMIID(sh4_int,0x420,11), /* TMU1 underflow */
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{GIPA(1),0x440},//sh4_TMU2_TUNI2 = KMIID(sh4_int,0x440,12), /* TMU2 underflow */
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{GIPA(1),0x460},//sh4_TMU2_TICPI2 = KMIID(sh4_int,0x460,13),
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//RTC
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{GIPA(0),0x480},//sh4_RTC_ATI = KMIID(sh4_int,0x480,14),
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{GIPA(0),0x4A0},//sh4_RTC_PRI = KMIID(sh4_int,0x4A0,15),
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{GIPA(0),0x4C0},//sh4_RTC_CUI = KMIID(sh4_int,0x4C0,16),
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//SCI
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{GIPB(1),0x4E0},//sh4_SCI1_ERI = KMIID(sh4_int,0x4E0,17),
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{GIPB(1),0x500},//sh4_SCI1_RXI = KMIID(sh4_int,0x500,18),
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{GIPB(1),0x520},//sh4_SCI1_TXI = KMIID(sh4_int,0x520,19),
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{GIPB(1),0x540},//sh4_SCI1_TEI = KMIID(sh4_int,0x540,29),
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//SCIF
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{GIPC(1),0x700},//sh4_SCIF_ERI = KMIID(sh4_int,0x700,21),
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{GIPC(1),0x720},//sh4_SCIF_RXI = KMIID(sh4_int,0x720,22),
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{GIPC(1),0x740},//sh4_SCIF_BRI = KMIID(sh4_int,0x740,23),
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{GIPC(1),0x760},//sh4_SCIF_TXI = KMIID(sh4_int,0x760,24),
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//WDT
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{GIPB(3),0x560},//sh4_WDT_ITI = KMIID(sh4_int,0x560,25),
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//REF
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{GIPB(2),0x580},//sh4_REF_RCMI = KMIID(sh4_int,0x580,26),
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{GIPA(2),0x5A0},//sh4_REF_ROVI = KMIID(sh4_int,0x5A0,27),
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};
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verify(sizeof(InterruptSourceList)==sizeof(InterruptSourceList2));
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memcpy(InterruptSourceList,InterruptSourceList2,sizeof(InterruptSourceList));
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}
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void interrupts_reset()
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@ -253,6 +247,5 @@ void interrupts_reset()
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void interrupts_term()
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{
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}
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@ -102,11 +102,22 @@ enum InterruptID
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void SetInterruptPend(InterruptID intr);
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void ResetInterruptPend(InterruptID intr);
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#define InterruptPend(intr,v) ((v)==0?ResetInterruptPend(intr):SetInterruptPend(intr))
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inline static void InterruptPend(InterruptID intr, u32 v) {
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if (v == 0)
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ResetInterruptPend(intr);
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else
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SetInterruptPend(intr);
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}
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void SetInterruptMask(InterruptID intr);
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void ResetInterruptMask(InterruptID intr);
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#define InterruptMask(intr,v) ((v)==0?ResetInterruptMask(intr):SetInterruptMask(intr))
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inline static void InterruptMask(InterruptID intr, u32 v)
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{
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if (v == 0)
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ResetInterruptMask(intr);
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else
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SetInterruptMask(intr);
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}
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int UpdateINTC();
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