diff --git a/core/hw/sh4/modules/tmu.cpp b/core/hw/sh4/modules/tmu.cpp index 944791614..c5da0f3f3 100644 --- a/core/hw/sh4/modules/tmu.cpp +++ b/core/hw/sh4/modules/tmu.cpp @@ -76,17 +76,17 @@ void UpdateTMU_i(u32 Cycles) u32 tmu_ch_base[3]; u64 tmu_ch_base64[3]; -u32 read_TMU_TCNTch(u32 ch) +static u32 read_TMU_TCNTch(u32 ch) { return tmu_ch_base[ch] - ((sh4_sched_now64() >> tmu_shift[ch])&tmu_mask[ch]); } -s64 read_TMU_TCNTch64(u32 ch) +static s64 read_TMU_TCNTch64(u32 ch) { return tmu_ch_base64[ch] - ((sh4_sched_now64() >> tmu_shift[ch])&tmu_mask64[ch]); } -void sched_chan_tick(int ch) +static void sched_chan_tick(int ch) { //schedule next interrupt //return TMU_TCOR(ch) << tmu_shift[ch]; @@ -105,10 +105,9 @@ void sched_chan_tick(int ch) sh4_sched_request(tmu_sched[ch], cycles ); else sh4_sched_request(tmu_sched[ch], -1); - //sched_tmu_cb } -void write_TMU_TCNTch(u32 ch, u32 data) +static void write_TMU_TCNTch(u32 ch, u32 data) { //u32 TCNT=read_TMU_TCNTch(ch); tmu_ch_base[ch]=data+((sh4_sched_now64()>>tmu_shift[ch])&tmu_mask[ch]); @@ -129,7 +128,7 @@ void write_TMU_TCNT(u32 addr, u32 data) write_TMU_TCNTch(ch,data); } -void turn_on_off_ch(u32 ch, bool on) +static void turn_on_off_ch(u32 ch, bool on) { u32 TCNT=read_TMU_TCNTch(ch); tmu_mask[ch]=on?0xFFFFFFFF:0x00000000; @@ -138,7 +137,7 @@ void turn_on_off_ch(u32 ch, bool on) } //Update internal counter registers -void UpdateTMUCounts(u32 reg) +static void UpdateTMUCounts(u32 reg) { InterruptPend(tmu_intID[reg],TMU_TCR(reg) & tmu_underflow); InterruptMask(tmu_intID[reg],TMU_TCR(reg) & tmu_UNIE); @@ -196,18 +195,18 @@ void TMU_TCR_write(u32 addr, u32 data) } //Chan 2 not used functions -u32 TMU_TCPR2_read(u32 addr) +static u32 TMU_TCPR2_read(u32 addr) { INFO_LOG(SH4, "Read from TMU_TCPR2 - this register should be not used on Dreamcast according to docs"); return 0; } -void TMU_TCPR2_write(u32 addr, u32 data) +static void TMU_TCPR2_write(u32 addr, u32 data) { INFO_LOG(SH4, "Write to TMU_TCPR2 - this register should be not used on Dreamcast according to docs, data=%d", data); } -void write_TMU_TSTR(u32 addr, u32 data) +static void write_TMU_TSTR(u32 addr, u32 data) { TMU_TSTR=data; //? @@ -216,7 +215,7 @@ void write_TMU_TSTR(u32 addr, u32 data) turn_on_off_ch(i,data&(1<>Shift)&0xF; } }; -//Can't be statically initialised because registers are dynamically allocated -InterptSourceList_Entry InterruptSourceList[28]; +static const InterptSourceList_Entry InterruptSourceList[28] = +{ + //IRL + {IRLP9,0x320},//sh4_IRL_9 = KMIID(sh4_int,0x320,0), + {IRLP11,0x360},//sh4_IRL_11 = KMIID(sh4_int,0x360,1), + {IRLP13,0x3A0},//sh4_IRL_13 = KMIID(sh4_int,0x3A0,2), + + //HUDI + {GIPC(0),0x600},//sh4_HUDI_HUDI = KMIID(sh4_int,0x600,3), /* H-UDI underflow */ + + //GPIO (missing on dc ?) + {GIPC(3),0x620},//sh4_GPIO_GPIOI = KMIID(sh4_int,0x620,4), + + //DMAC + {GIPC(2),0x640},//sh4_DMAC_DMTE0 = KMIID(sh4_int,0x640,5), + {GIPC(2),0x660},//sh4_DMAC_DMTE1 = KMIID(sh4_int,0x660,6), + {GIPC(2),0x680},//sh4_DMAC_DMTE2 = KMIID(sh4_int,0x680,7), + {GIPC(2),0x6A0},//sh4_DMAC_DMTE3 = KMIID(sh4_int,0x6A0,8), + {GIPC(2),0x6C0},//sh4_DMAC_DMAE = KMIID(sh4_int,0x6C0,9), + + //TMU + {GIPA(3),0x400},//sh4_TMU0_TUNI0 = KMIID(sh4_int,0x400,10), /* TMU0 underflow */ + {GIPA(2),0x420},//sh4_TMU1_TUNI1 = KMIID(sh4_int,0x420,11), /* TMU1 underflow */ + {GIPA(1),0x440},//sh4_TMU2_TUNI2 = KMIID(sh4_int,0x440,12), /* TMU2 underflow */ + {GIPA(1),0x460},//sh4_TMU2_TICPI2 = KMIID(sh4_int,0x460,13), + + //RTC + {GIPA(0),0x480},//sh4_RTC_ATI = KMIID(sh4_int,0x480,14), + {GIPA(0),0x4A0},//sh4_RTC_PRI = KMIID(sh4_int,0x4A0,15), + {GIPA(0),0x4C0},//sh4_RTC_CUI = KMIID(sh4_int,0x4C0,16), + + //SCI + {GIPB(1),0x4E0},//sh4_SCI1_ERI = KMIID(sh4_int,0x4E0,17), + {GIPB(1),0x500},//sh4_SCI1_RXI = KMIID(sh4_int,0x500,18), + {GIPB(1),0x520},//sh4_SCI1_TXI = KMIID(sh4_int,0x520,19), + {GIPB(1),0x540},//sh4_SCI1_TEI = KMIID(sh4_int,0x540,29), + + //SCIF + {GIPC(1),0x700},//sh4_SCIF_ERI = KMIID(sh4_int,0x700,21), + {GIPC(1),0x720},//sh4_SCIF_RXI = KMIID(sh4_int,0x720,22), + {GIPC(1),0x740},//sh4_SCIF_BRI = KMIID(sh4_int,0x740,23), + {GIPC(1),0x760},//sh4_SCIF_TXI = KMIID(sh4_int,0x760,24), + + //WDT + {GIPB(3),0x560},//sh4_WDT_ITI = KMIID(sh4_int,0x560,25), + + //REF + {GIPB(2),0x580},//sh4_REF_RCMI = KMIID(sh4_int,0x580,26), + {GIPA(2),0x5A0},//sh4_REF_ROVI = KMIID(sh4_int,0x5A0,27), +}; + //Maps siid -> EventID alignas(64) u16 InterruptEnvId[32] = { 0 }; @@ -48,8 +97,7 @@ alignas(64) u32 InterruptBit[32] = { 0 }; //Maps sh4 interrupt level to inclusive bitfield alignas(64) u32 InterruptLevelBit[16] = { 0 }; -bool Do_Interrupt(u32 intEvn); -bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect); +static bool Do_Interrupt(u32 intEvn); u32 interrupt_vpend; // Vector of pending interrupts u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts) @@ -142,7 +190,7 @@ void ResetInterruptMask(InterruptID intr) } -bool Do_Interrupt(u32 intEvn) +static bool Do_Interrupt(u32 intEvn) { CCN_INTEVT = intEvn; @@ -181,60 +229,6 @@ bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect) //Init/Res/Term void interrupts_init() { - InterptSourceList_Entry InterruptSourceList2[]= - { - //IRL - {IRLP9,0x320},//sh4_IRL_9 = KMIID(sh4_int,0x320,0), - {IRLP11,0x360},//sh4_IRL_11 = KMIID(sh4_int,0x360,1), - {IRLP13,0x3A0},//sh4_IRL_13 = KMIID(sh4_int,0x3A0,2), - - //HUDI - {GIPC(0),0x600},//sh4_HUDI_HUDI = KMIID(sh4_int,0x600,3), /* H-UDI underflow */ - - //GPIO (missing on dc ?) - {GIPC(3),0x620},//sh4_GPIO_GPIOI = KMIID(sh4_int,0x620,4), - - //DMAC - {GIPC(2),0x640},//sh4_DMAC_DMTE0 = KMIID(sh4_int,0x640,5), - {GIPC(2),0x660},//sh4_DMAC_DMTE1 = KMIID(sh4_int,0x660,6), - {GIPC(2),0x680},//sh4_DMAC_DMTE2 = KMIID(sh4_int,0x680,7), - {GIPC(2),0x6A0},//sh4_DMAC_DMTE3 = KMIID(sh4_int,0x6A0,8), - {GIPC(2),0x6C0},//sh4_DMAC_DMAE = KMIID(sh4_int,0x6C0,9), - - //TMU - {GIPA(3),0x400},//sh4_TMU0_TUNI0 = KMIID(sh4_int,0x400,10), /* TMU0 underflow */ - {GIPA(2),0x420},//sh4_TMU1_TUNI1 = KMIID(sh4_int,0x420,11), /* TMU1 underflow */ - {GIPA(1),0x440},//sh4_TMU2_TUNI2 = KMIID(sh4_int,0x440,12), /* TMU2 underflow */ - {GIPA(1),0x460},//sh4_TMU2_TICPI2 = KMIID(sh4_int,0x460,13), - - //RTC - {GIPA(0),0x480},//sh4_RTC_ATI = KMIID(sh4_int,0x480,14), - {GIPA(0),0x4A0},//sh4_RTC_PRI = KMIID(sh4_int,0x4A0,15), - {GIPA(0),0x4C0},//sh4_RTC_CUI = KMIID(sh4_int,0x4C0,16), - - //SCI - {GIPB(1),0x4E0},//sh4_SCI1_ERI = KMIID(sh4_int,0x4E0,17), - {GIPB(1),0x500},//sh4_SCI1_RXI = KMIID(sh4_int,0x500,18), - {GIPB(1),0x520},//sh4_SCI1_TXI = KMIID(sh4_int,0x520,19), - {GIPB(1),0x540},//sh4_SCI1_TEI = KMIID(sh4_int,0x540,29), - - //SCIF - {GIPC(1),0x700},//sh4_SCIF_ERI = KMIID(sh4_int,0x700,21), - {GIPC(1),0x720},//sh4_SCIF_RXI = KMIID(sh4_int,0x720,22), - {GIPC(1),0x740},//sh4_SCIF_BRI = KMIID(sh4_int,0x740,23), - {GIPC(1),0x760},//sh4_SCIF_TXI = KMIID(sh4_int,0x760,24), - - //WDT - {GIPB(3),0x560},//sh4_WDT_ITI = KMIID(sh4_int,0x560,25), - - //REF - {GIPB(2),0x580},//sh4_REF_RCMI = KMIID(sh4_int,0x580,26), - {GIPA(2),0x5A0},//sh4_REF_ROVI = KMIID(sh4_int,0x5A0,27), - }; - - verify(sizeof(InterruptSourceList)==sizeof(InterruptSourceList2)); - - memcpy(InterruptSourceList,InterruptSourceList2,sizeof(InterruptSourceList)); } void interrupts_reset() @@ -253,6 +247,5 @@ void interrupts_reset() void interrupts_term() { - } diff --git a/core/hw/sh4/sh4_interrupts.h b/core/hw/sh4/sh4_interrupts.h index 6299690b7..f793a8f63 100644 --- a/core/hw/sh4/sh4_interrupts.h +++ b/core/hw/sh4/sh4_interrupts.h @@ -102,11 +102,22 @@ enum InterruptID void SetInterruptPend(InterruptID intr); void ResetInterruptPend(InterruptID intr); -#define InterruptPend(intr,v) ((v)==0?ResetInterruptPend(intr):SetInterruptPend(intr)) +inline static void InterruptPend(InterruptID intr, u32 v) { + if (v == 0) + ResetInterruptPend(intr); + else + SetInterruptPend(intr); +} void SetInterruptMask(InterruptID intr); void ResetInterruptMask(InterruptID intr); -#define InterruptMask(intr,v) ((v)==0?ResetInterruptMask(intr):SetInterruptMask(intr)) +inline static void InterruptMask(InterruptID intr, u32 v) +{ + if (v == 0) + ResetInterruptMask(intr); + else + SetInterruptMask(intr); +} int UpdateINTC();