aica: use new logging
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5881791817
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cf6887a5d0
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@ -47,7 +47,7 @@ u32 ReadMem_aica_rtc(u32 addr,u32 sz)
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return 0;
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}
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printf("ReadMem_aica_rtc : invalid address\n");
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WARN_LOG(AICA, "ReadMem_aica_rtc : invalid address %x sz %d", addr, sz);
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return 0;
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}
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@ -123,12 +123,12 @@ void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
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if (addr==0x2C01)
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{
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VREG=data;
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printf("VREG = %02X\n",VREG);
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INFO_LOG(AICA, "VREG = %02X", VREG);
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}
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else if (addr==0x2C00)
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{
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ARMRST=data;
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printf("ARMRST = %02X\n",ARMRST);
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INFO_LOG(AICA, "ARMRST = %02X", ARMRST);
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ArmSetRST();
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}
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else
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@ -142,7 +142,7 @@ void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
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{
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VREG=(data>>8)&0xFF;
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ARMRST=data&0xFF;
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printf("VREG = %02X ARMRST %02X\n",VREG,ARMRST);
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INFO_LOG(AICA, "VREG = %02X ARMRST %02X", VREG, ARMRST);
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ArmSetRST();
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}
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else
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@ -216,17 +216,9 @@ void Write_SB_ADST(u32 addr, u32 data)
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u32 tmp=src;
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src=dst;
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dst=tmp;
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printf("**AICA DMA : SB_ADDIR==1: Not sure this works, please report if broken/missing sound or crash\n**");
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}
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WriteMemBlock_nommu_dma(dst,src,len);
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/*
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for (u32 i=0;i<len;i+=4)
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{
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u32 data=ReadMem32_nommu(src+i);
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WriteMem32_nommu(dst+i,data);
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}
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*/
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// idicate that dma is in progress
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SB_ADSUSP &= ~0x10;
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@ -273,10 +265,10 @@ void Write_SB_E1ST(u32 addr, u32 data)
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u32 t=src;
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src=dst;
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dst=t;
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printf("G2-EXT1 DMA : SB_E1DIR==1 DMA Read to 0x%X from 0x%X %d bytes\n",dst,src,len);
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DEBUG_LOG(AICA, "G2-EXT1 DMA : SB_E1DIR==1 DMA Read to 0x%X from 0x%X %d bytes", dst, src, len);
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}
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else
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printf("G2-EXT1 DMA : SB_E1DIR==0:DMA Write to 0x%X from 0x%X %d bytes\n",dst,src,len);
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DEBUG_LOG(AICA, "G2-EXT1 DMA : SB_E1DIR==0:DMA Write to 0x%X from 0x%X %d bytes", dst, src, len);
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WriteMemBlock_nommu_dma(dst,src,len);
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@ -316,10 +308,10 @@ void Write_SB_E2ST(u32 addr, u32 data)
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u32 t=src;
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src=dst;
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dst=t;
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printf("G2-EXT2 DMA : SB_E2DIR==1 DMA Read to 0x%X from 0x%X %d bytes\n",dst,src,len);
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DEBUG_LOG(AICA, "G2-EXT2 DMA : SB_E2DIR==1 DMA Read to 0x%X from 0x%X %d bytes", dst, src, len);
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}
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else
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printf("G2-EXT2 DMA : SB_E2DIR==0:DMA Write to 0x%X from 0x%X %d bytes\n",dst,src,len);
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DEBUG_LOG(AICA, "G2-EXT2 DMA : SB_E2DIR==0:DMA Write to 0x%X from 0x%X %d bytes", dst, src, len);
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WriteMemBlock_nommu_dma(dst,src,len);
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@ -36,7 +36,7 @@ public:
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void Compile(struct dsp_t *DSP)
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{
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this->DSP = DSP;
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//printf("DSPAssembler::DSPCompile recompiling for arm64 at %p\n", GetBuffer()->GetStartAddress<void*>());
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DEBUG_LOG(AICA_ARM, "DSPAssembler::DSPCompile recompiling for arm64 at %p", GetBuffer()->GetStartAddress<void*>());
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if (DSP->Stopped)
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{
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@ -101,7 +101,7 @@ public:
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#ifndef _ANDROID
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Instruction* instr_cur = GetBuffer()->GetEndAddress<Instruction*>();
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printf("DSP PROLOGUE\n");
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DEBUG_LOG(AICA_ARM, "DSP PROLOGUE");
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Disassemble(instr_start, instr_cur);
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instr_start = instr_cur;
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#endif
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@ -358,7 +358,7 @@ public:
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}
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#ifndef _ANDROID
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instr_cur = GetBuffer()->GetEndAddress<Instruction*>();
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printf("DSP STEP %d: %04x %04x %04x %04x\n", step, mpro[0], mpro[1], mpro[2], mpro[3]);
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DEBUG_LOG(AICA_ARM, "DSP STEP %d: %04x %04x %04x %04x", step, mpro[0], mpro[1], mpro[2], mpro[3]);
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Disassemble(instr_start, instr_cur);
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instr_start = instr_cur;
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#endif
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@ -380,7 +380,7 @@ public:
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Ret();
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#ifndef _ANDROID
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instr_cur = GetBuffer()->GetEndAddress<Instruction*>();
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printf("DSP EPILOGUE\n");
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DEBUG_LOG(AICA_ARM, "DSP EPILOGUE");
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Disassemble(instr_start, instr_cur);
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instr_start = instr_cur;
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#endif
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@ -486,9 +486,7 @@ private:
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Instruction* instr;
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for (instr = instr_start; instr < instr_end; instr += kInstructionSize) {
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decoder.Decode(instr);
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printf("\t %p:\t%s\n",
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reinterpret_cast<void*>(instr),
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disasm.GetOutput());
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DEBUG_LOG(AICA_ARM, " %p:\t%s", reinterpret_cast<void*>(instr), disasm.GetOutput());
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}
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}
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@ -8,9 +8,9 @@ using namespace std;
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#undef FAR
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//#define CLIP_WARN
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#define key_printf(...)
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#define aeg_printf(...)
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#define step_printf(...)
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#define key_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#define aeg_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#define step_printf(...) DEBUG_LOG(AICA, __VA_ARGS__)
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#ifdef CLIP_WARN
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#define clip_verify(x) verify(x)
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@ -490,7 +490,7 @@ struct ChannelEx
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StepStreamInitial(this);
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key_printf("[%d] KEY_ON %s @ %f Hz, loop : %d\n",Channel,stream_names[ChanData->PCMS],(44100.0*update_rate)/1024,ChanData->LPCTL);
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key_printf("[%p] KEY_ON %s @ %f Hz, loop : %d", this, stream_names[ccd->PCMS], (44100.0 * update_rate) / 1024, ccd->LPCTL);
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}
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else
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{
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@ -501,7 +501,7 @@ struct ChannelEx
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{
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if (AEG.state!=EG_Release)
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{
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key_printf("[%d] KEY_OFF -> Release\n",Channel);
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key_printf("[%p] KEY_OFF -> Release\n", this);
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SetAegState(EG_Release);
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//switch to release state
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}
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@ -862,7 +862,7 @@ void StreamStep(ChannelEx* ch)
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if ((ch->AEG.state==EG_Attack) && (CA>=ch->loop.LSA))
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{
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step_printf("[%d]LPSLNK : Switching to EG_Decay1 %X\n",Channel,AEG.GetValue());
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step_printf("[%p]LPSLNK : Switching to EG_Decay1 %X\n", ch, ch->AEG.GetValue());
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ch->SetAegState(EG_Decay1);
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}
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}
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@ -963,7 +963,7 @@ void AegStep(ChannelEx* ch)
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ch->AEG.SetValue(0);
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if (!ch->ccd->LPSLNK)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Decay1 %d\n",ch->AEG.GetValue());
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aeg_printf("[%p]AEG_step : Switching to EG_Decay1 %d\n", ch, ch->AEG.GetValue());
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ch->SetAegState(EG_Decay1);
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}
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}
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@ -975,7 +975,7 @@ void AegStep(ChannelEx* ch)
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ch->AEG.val+=ch->AEG.Decay1Rate;
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if (((u32)ch->AEG.GetValue())>=ch->AEG.Decay2Value)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Decay2 @ %x\n",ch->AEG.GetValue());
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aeg_printf("[%p]AEG_step : Switching to EG_Decay2 @ %x\n", ch, ch->AEG.GetValue());
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ch->SetAegState(EG_Decay2);
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}
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}
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@ -986,7 +986,7 @@ void AegStep(ChannelEx* ch)
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ch->AEG.val+=ch->AEG.Decay2Rate;
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if (ch->AEG.GetValue()>=0x3FF)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Release @ %x\n",ch->AEG.GetValue());
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aeg_printf("[%p]AEG_step : Switching to EG_Release @ %x\n", ch, ch->AEG.GetValue());
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ch->AEG.SetValue(0x3FF);
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ch->SetAegState(EG_Release);
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}
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@ -998,7 +998,7 @@ void AegStep(ChannelEx* ch)
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if (ch->AEG.GetValue()>=0x3FF)
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{
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aeg_printf("[%d]AEG_step : EG_Release End @ %x\n",ch->AEG.GetValue());
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aeg_printf("[%p]AEG_step : EG_Release End @ %x\n", ch, ch->AEG.GetValue());
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ch->AEG.SetValue(0x3FF); // TODO: mnn, should we do anything about it running wild ?
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ch->disable(); // TODO: Is this ok here? It's a speed optimisation (since the channel is muted)
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}
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@ -157,7 +157,7 @@ void armv_end(void* codestart, u32 cycl)
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Instruction* instr;
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for (instr = instr_start; instr < instr_end; instr += kInstructionSize) {
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decoder.Decode(instr);
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printf("arm64 arec\t %p:\t%s\n",
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DEBUG_LOG(AICA_ARM, "arm64 arec\t %p:\t%s",
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reinterpret_cast<void*>(instr),
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disasm.GetOutput());
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}
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@ -206,7 +206,7 @@ class android_buf : public std::stringbuf
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{
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public:
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virtual int sync() override {
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LOGI("ARM7: %s\n", this->str().c_str());
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DEBUG_LOG(AICA_ARM, "ARM7: %s", this->str().c_str());
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str("");
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return 0;
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@ -7,11 +7,7 @@
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#define C_CORE
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#if 0
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#define arm_printf printf
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#else
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void arm_printf(...) { }
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#endif
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#define arm_printf(...) DEBUG_LOG(AICA_ARM, __VA_ARGS__)
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//#define CPUReadHalfWordQuick(addr) arm_ReadMem16(addr & 0x7FFFFF)
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#define CPUReadMemoryQuick(addr) (*(u32*)&aica_ram[addr&ARAM_MASK])
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@ -224,7 +220,7 @@ void CPUSwitchMode(int mode, bool saveState, bool breakLoop)
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reg[17].I = reg[SPSR_UND].I;
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break;
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default:
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printf("Unsupported ARM mode %02x\n", mode);
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ERROR_LOG(AICA_ARM, "Unsupported ARM mode %02x", mode);
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die("Arm error..");
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break;
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}
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@ -298,7 +294,7 @@ void CPUSoftwareInterrupt(int comment)
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void CPUUndefinedException()
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{
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printf("arm7: CPUUndefinedException(). SOMETHING WENT WRONG\n");
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WARN_LOG(AICA_ARM, "arm7: CPUUndefinedException(). SOMETHING WENT WRONG");
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u32 PC = reg[R15_ARM_NEXT].I+4;
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CPUSwitchMode(0x1b, true, false);
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reg[14].I = PC;
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@ -1345,7 +1341,7 @@ void DumpRegs(const char* output)
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void DYNACALL PrintOp(u32 opcd)
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{
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printf("%08X\n",opcd);
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DEBUG_LOG(AICA_ARM, "%08X", opcd);
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}
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void armv_imm_to_reg(u32 regn, u32 imm)
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