diff --git a/core/hw/aica/aica_if.cpp b/core/hw/aica/aica_if.cpp index c1799793b..e66171a5f 100644 --- a/core/hw/aica/aica_if.cpp +++ b/core/hw/aica/aica_if.cpp @@ -47,7 +47,7 @@ u32 ReadMem_aica_rtc(u32 addr,u32 sz) return 0; } - printf("ReadMem_aica_rtc : invalid address\n"); + WARN_LOG(AICA, "ReadMem_aica_rtc : invalid address %x sz %d", addr, sz); return 0; } @@ -123,12 +123,12 @@ void WriteMem_aica_reg(u32 addr,u32 data,u32 sz) if (addr==0x2C01) { VREG=data; - printf("VREG = %02X\n",VREG); + INFO_LOG(AICA, "VREG = %02X", VREG); } else if (addr==0x2C00) { ARMRST=data; - printf("ARMRST = %02X\n",ARMRST); + INFO_LOG(AICA, "ARMRST = %02X", ARMRST); ArmSetRST(); } else @@ -142,7 +142,7 @@ void WriteMem_aica_reg(u32 addr,u32 data,u32 sz) { VREG=(data>>8)&0xFF; ARMRST=data&0xFF; - printf("VREG = %02X ARMRST %02X\n",VREG,ARMRST); + INFO_LOG(AICA, "VREG = %02X ARMRST %02X", VREG, ARMRST); ArmSetRST(); } else @@ -216,17 +216,9 @@ void Write_SB_ADST(u32 addr, u32 data) u32 tmp=src; src=dst; dst=tmp; - printf("**AICA DMA : SB_ADDIR==1: Not sure this works, please report if broken/missing sound or crash\n**"); } WriteMemBlock_nommu_dma(dst,src,len); - /* - for (u32 i=0;iDSP = DSP; - //printf("DSPAssembler::DSPCompile recompiling for arm64 at %p\n", GetBuffer()->GetStartAddress()); + DEBUG_LOG(AICA_ARM, "DSPAssembler::DSPCompile recompiling for arm64 at %p", GetBuffer()->GetStartAddress()); if (DSP->Stopped) { @@ -101,7 +101,7 @@ public: #ifndef _ANDROID Instruction* instr_cur = GetBuffer()->GetEndAddress(); - printf("DSP PROLOGUE\n"); + DEBUG_LOG(AICA_ARM, "DSP PROLOGUE"); Disassemble(instr_start, instr_cur); instr_start = instr_cur; #endif @@ -358,7 +358,7 @@ public: } #ifndef _ANDROID instr_cur = GetBuffer()->GetEndAddress(); - printf("DSP STEP %d: %04x %04x %04x %04x\n", step, mpro[0], mpro[1], mpro[2], mpro[3]); + DEBUG_LOG(AICA_ARM, "DSP STEP %d: %04x %04x %04x %04x", step, mpro[0], mpro[1], mpro[2], mpro[3]); Disassemble(instr_start, instr_cur); instr_start = instr_cur; #endif @@ -380,7 +380,7 @@ public: Ret(); #ifndef _ANDROID instr_cur = GetBuffer()->GetEndAddress(); - printf("DSP EPILOGUE\n"); + DEBUG_LOG(AICA_ARM, "DSP EPILOGUE"); Disassemble(instr_start, instr_cur); instr_start = instr_cur; #endif @@ -486,9 +486,7 @@ private: Instruction* instr; for (instr = instr_start; instr < instr_end; instr += kInstructionSize) { decoder.Decode(instr); - printf("\t %p:\t%s\n", - reinterpret_cast(instr), - disasm.GetOutput()); + DEBUG_LOG(AICA_ARM, " %p:\t%s", reinterpret_cast(instr), disasm.GetOutput()); } } diff --git a/core/hw/aica/sgc_if.cpp b/core/hw/aica/sgc_if.cpp index 4b970ee32..20e52f0a9 100755 --- a/core/hw/aica/sgc_if.cpp +++ b/core/hw/aica/sgc_if.cpp @@ -8,9 +8,9 @@ using namespace std; #undef FAR //#define CLIP_WARN -#define key_printf(...) -#define aeg_printf(...) -#define step_printf(...) +#define key_printf(...) DEBUG_LOG(AICA, __VA_ARGS__) +#define aeg_printf(...) DEBUG_LOG(AICA, __VA_ARGS__) +#define step_printf(...) DEBUG_LOG(AICA, __VA_ARGS__) #ifdef CLIP_WARN #define clip_verify(x) verify(x) @@ -490,7 +490,7 @@ struct ChannelEx StepStreamInitial(this); - key_printf("[%d] KEY_ON %s @ %f Hz, loop : %d\n",Channel,stream_names[ChanData->PCMS],(44100.0*update_rate)/1024,ChanData->LPCTL); + key_printf("[%p] KEY_ON %s @ %f Hz, loop : %d", this, stream_names[ccd->PCMS], (44100.0 * update_rate) / 1024, ccd->LPCTL); } else { @@ -501,7 +501,7 @@ struct ChannelEx { if (AEG.state!=EG_Release) { - key_printf("[%d] KEY_OFF -> Release\n",Channel); + key_printf("[%p] KEY_OFF -> Release\n", this); SetAegState(EG_Release); //switch to release state } @@ -862,7 +862,7 @@ void StreamStep(ChannelEx* ch) if ((ch->AEG.state==EG_Attack) && (CA>=ch->loop.LSA)) { - step_printf("[%d]LPSLNK : Switching to EG_Decay1 %X\n",Channel,AEG.GetValue()); + step_printf("[%p]LPSLNK : Switching to EG_Decay1 %X\n", ch, ch->AEG.GetValue()); ch->SetAegState(EG_Decay1); } } @@ -963,7 +963,7 @@ void AegStep(ChannelEx* ch) ch->AEG.SetValue(0); if (!ch->ccd->LPSLNK) { - aeg_printf("[%d]AEG_step : Switching to EG_Decay1 %d\n",ch->AEG.GetValue()); + aeg_printf("[%p]AEG_step : Switching to EG_Decay1 %d\n", ch, ch->AEG.GetValue()); ch->SetAegState(EG_Decay1); } } @@ -975,7 +975,7 @@ void AegStep(ChannelEx* ch) ch->AEG.val+=ch->AEG.Decay1Rate; if (((u32)ch->AEG.GetValue())>=ch->AEG.Decay2Value) { - aeg_printf("[%d]AEG_step : Switching to EG_Decay2 @ %x\n",ch->AEG.GetValue()); + aeg_printf("[%p]AEG_step : Switching to EG_Decay2 @ %x\n", ch, ch->AEG.GetValue()); ch->SetAegState(EG_Decay2); } } @@ -986,7 +986,7 @@ void AegStep(ChannelEx* ch) ch->AEG.val+=ch->AEG.Decay2Rate; if (ch->AEG.GetValue()>=0x3FF) { - aeg_printf("[%d]AEG_step : Switching to EG_Release @ %x\n",ch->AEG.GetValue()); + aeg_printf("[%p]AEG_step : Switching to EG_Release @ %x\n", ch, ch->AEG.GetValue()); ch->AEG.SetValue(0x3FF); ch->SetAegState(EG_Release); } @@ -998,7 +998,7 @@ void AegStep(ChannelEx* ch) if (ch->AEG.GetValue()>=0x3FF) { - aeg_printf("[%d]AEG_step : EG_Release End @ %x\n",ch->AEG.GetValue()); + aeg_printf("[%p]AEG_step : EG_Release End @ %x\n", ch, ch->AEG.GetValue()); ch->AEG.SetValue(0x3FF); // TODO: mnn, should we do anything about it running wild ? ch->disable(); // TODO: Is this ok here? It's a speed optimisation (since the channel is muted) } diff --git a/core/hw/arm7/arm64.cpp b/core/hw/arm7/arm64.cpp index e712855bd..5e86900ca 100644 --- a/core/hw/arm7/arm64.cpp +++ b/core/hw/arm7/arm64.cpp @@ -157,7 +157,7 @@ void armv_end(void* codestart, u32 cycl) Instruction* instr; for (instr = instr_start; instr < instr_end; instr += kInstructionSize) { decoder.Decode(instr); - printf("arm64 arec\t %p:\t%s\n", + DEBUG_LOG(AICA_ARM, "arm64 arec\t %p:\t%s", reinterpret_cast(instr), disasm.GetOutput()); } @@ -206,7 +206,7 @@ class android_buf : public std::stringbuf { public: virtual int sync() override { - LOGI("ARM7: %s\n", this->str().c_str()); + DEBUG_LOG(AICA_ARM, "ARM7: %s", this->str().c_str()); str(""); return 0; diff --git a/core/hw/arm7/arm7.cpp b/core/hw/arm7/arm7.cpp index 4d5f0e117..b79a273de 100644 --- a/core/hw/arm7/arm7.cpp +++ b/core/hw/arm7/arm7.cpp @@ -7,11 +7,7 @@ #define C_CORE -#if 0 - #define arm_printf printf -#else - void arm_printf(...) { } -#endif +#define arm_printf(...) DEBUG_LOG(AICA_ARM, __VA_ARGS__) //#define CPUReadHalfWordQuick(addr) arm_ReadMem16(addr & 0x7FFFFF) #define CPUReadMemoryQuick(addr) (*(u32*)&aica_ram[addr&ARAM_MASK]) @@ -224,7 +220,7 @@ void CPUSwitchMode(int mode, bool saveState, bool breakLoop) reg[17].I = reg[SPSR_UND].I; break; default: - printf("Unsupported ARM mode %02x\n", mode); + ERROR_LOG(AICA_ARM, "Unsupported ARM mode %02x", mode); die("Arm error.."); break; } @@ -298,7 +294,7 @@ void CPUSoftwareInterrupt(int comment) void CPUUndefinedException() { - printf("arm7: CPUUndefinedException(). SOMETHING WENT WRONG\n"); + WARN_LOG(AICA_ARM, "arm7: CPUUndefinedException(). SOMETHING WENT WRONG"); u32 PC = reg[R15_ARM_NEXT].I+4; CPUSwitchMode(0x1b, true, false); reg[14].I = PC; @@ -1345,7 +1341,7 @@ void DumpRegs(const char* output) void DYNACALL PrintOp(u32 opcd) { - printf("%08X\n",opcd); + DEBUG_LOG(AICA_ARM, "%08X", opcd); } void armv_imm_to_reg(u32 regn, u32 imm)