arm: aica RAM overflow crash with arm32 and arm64 recs
Move target platform #def's to build.h Fix Sturmwind and Volgarr crashes
This commit is contained in:
Flyinghead
parent
0a301a4758
commit
ca750ae454
109
core/build.h
109
core/build.h
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@ -286,10 +286,6 @@
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#define FEAT_HAS_SOFTREND BUILD_COMPILER == COMPILER_VC //GCC wants us to enable sse4 globaly to enable intrins
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#endif
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#define RAM_SIZE_MAX (32*1024*1024)
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#define VRAM_SIZE_MAX (16*1024*1024)
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#define ARAM_SIZE_MAX (8*1024*1024)
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//Depricated build configs
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#ifdef HOST_NO_REC
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#error Dont use HOST_NO_REC
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@ -298,3 +294,108 @@
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#ifdef HOST_NO_AREC
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#error Dont use HOST_NO_AREC
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#endif
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// TARGET PLATFORM
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#define RAM_SIZE_MAX (32*1024*1024)
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#define VRAM_SIZE_MAX (16*1024*1024)
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#define ARAM_SIZE_MAX (8*1024*1024)
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#if (DC_PLATFORM==DC_PLATFORM_DREAMCAST)
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#define BUILD_DREAMCAST 1
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//DC : 16 mb ram, 8 mb vram, 2 mb aram, 2 mb bios, 128k flash
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#define RAM_SIZE (16*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (2*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define FLASH_SIZE (128*1024)
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#define ROM_PREFIX "dc_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 0
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#elif (DC_PLATFORM==DC_PLATFORM_DEV_UNIT)
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#define BUILD_DEV_UNIT 1
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//Devkit : 32 mb ram, 8? mb vram, 2? mb aram, 2? mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (2*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define FLASH_SIZE (128*1024)
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#define ROM_PREFIX "hkt_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 0
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#elif (DC_PLATFORM==DC_PLATFORM_NAOMI)
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//Naomi : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (16*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define BBSRAM_SIZE (32*1024)
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#define ROM_PREFIX "naomi_"
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#define ROM_NAMES ";epr-21576d.bin"
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#define NVR_OPTIONAL 1
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#elif (DC_PLATFORM==DC_PLATFORM_NAOMI2)
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//Naomi2 : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (16*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define BBSRAM_SIZE (32*1024)
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#define ROM_PREFIX "n2_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 1
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#elif (DC_PLATFORM==DC_PLATFORM_ATOMISWAVE)
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#define BUILD_ATOMISWAVE 1
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//Atomiswave : 16 mb ram, 8 mb vram, 8 mb aram, 128kb bios on flash, 128kb battery-backed ram
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#define RAM_SIZE (16*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (128*1024)
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#define BBSRAM_SIZE (128*1024)
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#define ROM_PREFIX "aw_"
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#define ROM_NAMES ";bios.ic23_l"
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#define NVR_OPTIONAL 1
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#else
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#error invalid build config
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#endif
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#define RAM_MASK (RAM_SIZE-1)
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#define VRAM_MASK (VRAM_SIZE-1)
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#define ARAM_MASK (ARAM_SIZE-1)
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#define BIOS_MASK (BIOS_SIZE-1)
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#ifdef FLASH_SIZE
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#define FLASH_MASK (FLASH_SIZE-1)
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#endif
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#ifdef BBSRAM_SIZE
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#define BBSRAM_MASK (BBSRAM_SIZE-1)
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#endif
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#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs
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#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs
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#define ADAC_CLOCK (AICA_CORE_CLOCK/2) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs
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#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM
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#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM
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#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200)
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#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip
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#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls
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@ -499,8 +499,13 @@ __asm__ (
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".hidden arm_dispatch \n"
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"arm_dispatch: \n\t"
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"ldp w0, w1, [x28, #184] \n\t" // load Next PC, interrupt
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"ubfx w2, w0, #2, #21 \n\t" // w2 = pc >> 2. Note: assuming address space <= 8 MB (23 bits)
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#if ARAM_SIZE == 2*1024*1024
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"ubfx w2, w0, #2, #19 \n\t" // w2 = pc >> 2. Note: assuming address space == 2 MB (21 bits)
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#elif ARAM_SIZE == 8*1024*1024
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"ubfx w2, w0, #2, #21 \n\t" // w2 = pc >> 2. Note: assuming address space == 8 MB (23 bits)
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#else
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#error Unsupported AICA RAM size
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#endif
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"cbnz w1, arm_dofiq \n\t" // if interrupt pending, handle it
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"add x2, x26, x2, lsl #3 \n\t" // x2 = EntryPoints + pc << 1
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@ -58,6 +58,7 @@ bkpt #0
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bkpt
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#endif
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ubfx r0,r3,#5,#19 @ get vram offset
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@ should be only 18 bits for 8MB VRAM but it wraps around on dc
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add r3,r1,#0x04000000 @ get vram ptr from r1, part 1
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add r3,#512 @ get ram ptr from r1, part 2
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add r3,r0,lsl #5 @ ram + offset
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@ -180,6 +181,7 @@ CSYM(no_update): @ next_pc _MUST_ be on r4 *R4 NOT R0 anymore*
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#if RAM_SIZE_MAX == 33554432
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sub r2,r8,#0x4100000
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ubfx r1,r4,#1,#24 @ 24+1 bits: 32 MB
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@ RAM wraps around so if actual RAM size is 16MB, we won't overflow
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#elif RAM_SIZE_MAX == 16777216
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sub r2,r8,#0x2100000
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ubfx r1,r4,#1,#23 @ 23+1 bits: 16 MB
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@ -241,7 +243,13 @@ HIDDEN(arm_dispatch)
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CSYM(arm_dispatch):
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ldrd r0,r1,[r8,#184] @load: Next PC, interrupt
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#if ARAM_SIZE == 2*1024*1024
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ubfx r2,r0,#2,#19 @ assuming 2 MB address space max (21 bits)
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#elif ARAM_SIZE == 8*1024*1024
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ubfx r2,r0,#2,#21 @ assuming 8 MB address space max (23 bits)
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#else
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#error Unsupported AICA RAM size
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#endif
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cmp r1,#0
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bne arm_dofiq
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100
core/types.h
100
core/types.h
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@ -204,106 +204,6 @@ struct vram_block
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void* userdata;
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};
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#if (DC_PLATFORM==DC_PLATFORM_DREAMCAST)
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#define BUILD_DREAMCAST 1
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//DC : 16 mb ram, 8 mb vram, 2 mb aram, 2 mb bios, 128k flash
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#define RAM_SIZE (16*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (2*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define FLASH_SIZE (128*1024)
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#define ROM_PREFIX "dc_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 0
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#elif (DC_PLATFORM==DC_PLATFORM_DEV_UNIT)
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#define BUILD_DEV_UNIT 1
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//Devkit : 32 mb ram, 8? mb vram, 2? mb aram, 2? mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (2*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define FLASH_SIZE (128*1024)
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#define ROM_PREFIX "hkt_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 0
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#elif (DC_PLATFORM==DC_PLATFORM_NAOMI)
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//Naomi : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (16*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define BBSRAM_SIZE (32*1024)
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#define ROM_PREFIX "naomi_"
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#define ROM_NAMES ";epr-21576d.bin"
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#define NVR_OPTIONAL 1
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#elif (DC_PLATFORM==DC_PLATFORM_NAOMI2)
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//Naomi2 : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash
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#define RAM_SIZE (32*1024*1024)
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#define VRAM_SIZE (16*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (2*1024*1024)
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#define BBSRAM_SIZE (32*1024)
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#define ROM_PREFIX "n2_"
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#define ROM_NAMES
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#define NVR_OPTIONAL 1
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#elif (DC_PLATFORM==DC_PLATFORM_ATOMISWAVE)
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#define BUILD_ATOMISWAVE 1
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//Atomiswave : 16 mb ram, 8 mb vram, 8 mb aram, 128kb bios on flash, 128kb battery-backed ram
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#define RAM_SIZE (16*1024*1024)
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#define VRAM_SIZE (8*1024*1024)
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#define ARAM_SIZE (8*1024*1024)
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#define BIOS_SIZE (128*1024)
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#define BBSRAM_SIZE (128*1024)
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#define ROM_PREFIX "aw_"
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#define ROM_NAMES ";bios.ic23_l"
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#define NVR_OPTIONAL 1
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#else
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#error invalid build config
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#endif
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#define RAM_MASK (RAM_SIZE-1)
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#define VRAM_MASK (VRAM_SIZE-1)
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#define ARAM_MASK (ARAM_SIZE-1)
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#define BIOS_MASK (BIOS_SIZE-1)
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#ifdef FLASH_SIZE
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#define FLASH_MASK (FLASH_SIZE-1)
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#endif
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#ifdef BBSRAM_SIZE
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#define BBSRAM_MASK (BBSRAM_SIZE-1)
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#endif
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#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs
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#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs
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#define ADAC_CLOCK (AICA_CORE_CLOCK/2) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs
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#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM
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#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM
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#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200)
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#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip
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#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls
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enum ndc_error_codes
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{
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rv_ok = 0, //no error
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