From ca750ae454334457dd5315af8c9e71c22af26658 Mon Sep 17 00:00:00 2001 From: Flyinghead Date: Thu, 28 Mar 2019 11:41:48 +0100 Subject: [PATCH] arm: aica RAM overflow crash with arm32 and arm64 recs Move target platform #def's to build.h Fix Sturmwind and Volgarr crashes --- core/build.h | 109 ++++++++++++++++++++++++++++++++++++++-- core/hw/arm7/arm64.cpp | 9 +++- core/rec-ARM/ngen_arm.S | 8 +++ core/types.h | 100 ------------------------------------ 4 files changed, 120 insertions(+), 106 deletions(-) diff --git a/core/build.h b/core/build.h index c3dc80b9a..a9a9777dd 100755 --- a/core/build.h +++ b/core/build.h @@ -286,10 +286,6 @@ #define FEAT_HAS_SOFTREND BUILD_COMPILER == COMPILER_VC //GCC wants us to enable sse4 globaly to enable intrins #endif -#define RAM_SIZE_MAX (32*1024*1024) -#define VRAM_SIZE_MAX (16*1024*1024) -#define ARAM_SIZE_MAX (8*1024*1024) - //Depricated build configs #ifdef HOST_NO_REC #error Dont use HOST_NO_REC @@ -298,3 +294,108 @@ #ifdef HOST_NO_AREC #error Dont use HOST_NO_AREC #endif + +// TARGET PLATFORM + +#define RAM_SIZE_MAX (32*1024*1024) +#define VRAM_SIZE_MAX (16*1024*1024) +#define ARAM_SIZE_MAX (8*1024*1024) + +#if (DC_PLATFORM==DC_PLATFORM_DREAMCAST) + + #define BUILD_DREAMCAST 1 + + //DC : 16 mb ram, 8 mb vram, 2 mb aram, 2 mb bios, 128k flash + #define RAM_SIZE (16*1024*1024) + #define VRAM_SIZE (8*1024*1024) + #define ARAM_SIZE (2*1024*1024) + #define BIOS_SIZE (2*1024*1024) + #define FLASH_SIZE (128*1024) + + #define ROM_PREFIX "dc_" + #define ROM_NAMES + #define NVR_OPTIONAL 0 + +#elif (DC_PLATFORM==DC_PLATFORM_DEV_UNIT) + + #define BUILD_DEV_UNIT 1 + + //Devkit : 32 mb ram, 8? mb vram, 2? mb aram, 2? mb bios, ? flash + #define RAM_SIZE (32*1024*1024) + #define VRAM_SIZE (8*1024*1024) + #define ARAM_SIZE (2*1024*1024) + #define BIOS_SIZE (2*1024*1024) + #define FLASH_SIZE (128*1024) + + #define ROM_PREFIX "hkt_" + #define ROM_NAMES + #define NVR_OPTIONAL 0 + +#elif (DC_PLATFORM==DC_PLATFORM_NAOMI) + + //Naomi : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash + #define RAM_SIZE (32*1024*1024) + #define VRAM_SIZE (16*1024*1024) + #define ARAM_SIZE (8*1024*1024) + #define BIOS_SIZE (2*1024*1024) + #define BBSRAM_SIZE (32*1024) + + #define ROM_PREFIX "naomi_" + #define ROM_NAMES ";epr-21576d.bin" + #define NVR_OPTIONAL 1 + +#elif (DC_PLATFORM==DC_PLATFORM_NAOMI2) + + //Naomi2 : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash + #define RAM_SIZE (32*1024*1024) + #define VRAM_SIZE (16*1024*1024) + #define ARAM_SIZE (8*1024*1024) + #define BIOS_SIZE (2*1024*1024) + #define BBSRAM_SIZE (32*1024) + + #define ROM_PREFIX "n2_" + #define ROM_NAMES + #define NVR_OPTIONAL 1 + +#elif (DC_PLATFORM==DC_PLATFORM_ATOMISWAVE) + + #define BUILD_ATOMISWAVE 1 + + //Atomiswave : 16 mb ram, 8 mb vram, 8 mb aram, 128kb bios on flash, 128kb battery-backed ram + #define RAM_SIZE (16*1024*1024) + #define VRAM_SIZE (8*1024*1024) + #define ARAM_SIZE (8*1024*1024) + #define BIOS_SIZE (128*1024) + #define BBSRAM_SIZE (128*1024) + + #define ROM_PREFIX "aw_" + #define ROM_NAMES ";bios.ic23_l" + #define NVR_OPTIONAL 1 + +#else + #error invalid build config +#endif + +#define RAM_MASK (RAM_SIZE-1) +#define VRAM_MASK (VRAM_SIZE-1) +#define ARAM_MASK (ARAM_SIZE-1) +#define BIOS_MASK (BIOS_SIZE-1) + +#ifdef FLASH_SIZE +#define FLASH_MASK (FLASH_SIZE-1) +#endif + +#ifdef BBSRAM_SIZE +#define BBSRAM_MASK (BBSRAM_SIZE-1) +#endif + +#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs + +#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs +#define ADAC_CLOCK (AICA_CORE_CLOCK/2) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs +#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM +#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM +#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200) +#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip +#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls + diff --git a/core/hw/arm7/arm64.cpp b/core/hw/arm7/arm64.cpp index bcaf7d70c..89e57ab66 100644 --- a/core/hw/arm7/arm64.cpp +++ b/core/hw/arm7/arm64.cpp @@ -499,8 +499,13 @@ __asm__ ( ".hidden arm_dispatch \n" "arm_dispatch: \n\t" "ldp w0, w1, [x28, #184] \n\t" // load Next PC, interrupt - - "ubfx w2, w0, #2, #21 \n\t" // w2 = pc >> 2. Note: assuming address space <= 8 MB (23 bits) +#if ARAM_SIZE == 2*1024*1024 + "ubfx w2, w0, #2, #19 \n\t" // w2 = pc >> 2. Note: assuming address space == 2 MB (21 bits) +#elif ARAM_SIZE == 8*1024*1024 + "ubfx w2, w0, #2, #21 \n\t" // w2 = pc >> 2. Note: assuming address space == 8 MB (23 bits) +#else +#error Unsupported AICA RAM size +#endif "cbnz w1, arm_dofiq \n\t" // if interrupt pending, handle it "add x2, x26, x2, lsl #3 \n\t" // x2 = EntryPoints + pc << 1 diff --git a/core/rec-ARM/ngen_arm.S b/core/rec-ARM/ngen_arm.S index 61ab59e82..55fbc8fad 100644 --- a/core/rec-ARM/ngen_arm.S +++ b/core/rec-ARM/ngen_arm.S @@ -58,6 +58,7 @@ bkpt #0 bkpt #endif ubfx r0,r3,#5,#19 @ get vram offset + @ should be only 18 bits for 8MB VRAM but it wraps around on dc add r3,r1,#0x04000000 @ get vram ptr from r1, part 1 add r3,#512 @ get ram ptr from r1, part 2 add r3,r0,lsl #5 @ ram + offset @@ -180,6 +181,7 @@ CSYM(no_update): @ next_pc _MUST_ be on r4 *R4 NOT R0 anymore* #if RAM_SIZE_MAX == 33554432 sub r2,r8,#0x4100000 ubfx r1,r4,#1,#24 @ 24+1 bits: 32 MB + @ RAM wraps around so if actual RAM size is 16MB, we won't overflow #elif RAM_SIZE_MAX == 16777216 sub r2,r8,#0x2100000 ubfx r1,r4,#1,#23 @ 23+1 bits: 16 MB @@ -241,7 +243,13 @@ HIDDEN(arm_dispatch) CSYM(arm_dispatch): ldrd r0,r1,[r8,#184] @load: Next PC, interrupt +#if ARAM_SIZE == 2*1024*1024 + ubfx r2,r0,#2,#19 @ assuming 2 MB address space max (21 bits) +#elif ARAM_SIZE == 8*1024*1024 ubfx r2,r0,#2,#21 @ assuming 8 MB address space max (23 bits) +#else +#error Unsupported AICA RAM size +#endif cmp r1,#0 bne arm_dofiq diff --git a/core/types.h b/core/types.h index a893d27e2..b3f809dc3 100644 --- a/core/types.h +++ b/core/types.h @@ -204,106 +204,6 @@ struct vram_block void* userdata; }; - -#if (DC_PLATFORM==DC_PLATFORM_DREAMCAST) - - #define BUILD_DREAMCAST 1 - - //DC : 16 mb ram, 8 mb vram, 2 mb aram, 2 mb bios, 128k flash - #define RAM_SIZE (16*1024*1024) - #define VRAM_SIZE (8*1024*1024) - #define ARAM_SIZE (2*1024*1024) - #define BIOS_SIZE (2*1024*1024) - #define FLASH_SIZE (128*1024) - - #define ROM_PREFIX "dc_" - #define ROM_NAMES - #define NVR_OPTIONAL 0 - -#elif (DC_PLATFORM==DC_PLATFORM_DEV_UNIT) - - #define BUILD_DEV_UNIT 1 - - //Devkit : 32 mb ram, 8? mb vram, 2? mb aram, 2? mb bios, ? flash - #define RAM_SIZE (32*1024*1024) - #define VRAM_SIZE (8*1024*1024) - #define ARAM_SIZE (2*1024*1024) - #define BIOS_SIZE (2*1024*1024) - #define FLASH_SIZE (128*1024) - - #define ROM_PREFIX "hkt_" - #define ROM_NAMES - #define NVR_OPTIONAL 0 - -#elif (DC_PLATFORM==DC_PLATFORM_NAOMI) - - //Naomi : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash - #define RAM_SIZE (32*1024*1024) - #define VRAM_SIZE (16*1024*1024) - #define ARAM_SIZE (8*1024*1024) - #define BIOS_SIZE (2*1024*1024) - #define BBSRAM_SIZE (32*1024) - - #define ROM_PREFIX "naomi_" - #define ROM_NAMES ";epr-21576d.bin" - #define NVR_OPTIONAL 1 - -#elif (DC_PLATFORM==DC_PLATFORM_NAOMI2) - - //Naomi2 : 32 mb ram, 16 mb vram, 8 mb aram, 2 mb bios, ? flash - #define RAM_SIZE (32*1024*1024) - #define VRAM_SIZE (16*1024*1024) - #define ARAM_SIZE (8*1024*1024) - #define BIOS_SIZE (2*1024*1024) - #define BBSRAM_SIZE (32*1024) - - #define ROM_PREFIX "n2_" - #define ROM_NAMES - #define NVR_OPTIONAL 1 - -#elif (DC_PLATFORM==DC_PLATFORM_ATOMISWAVE) - - #define BUILD_ATOMISWAVE 1 - - //Atomiswave : 16 mb ram, 8 mb vram, 8 mb aram, 128kb bios on flash, 128kb battery-backed ram - #define RAM_SIZE (16*1024*1024) - #define VRAM_SIZE (8*1024*1024) - #define ARAM_SIZE (8*1024*1024) - #define BIOS_SIZE (128*1024) - #define BBSRAM_SIZE (128*1024) - - #define ROM_PREFIX "aw_" - #define ROM_NAMES ";bios.ic23_l" - #define NVR_OPTIONAL 1 - -#else - #error invalid build config -#endif - -#define RAM_MASK (RAM_SIZE-1) -#define VRAM_MASK (VRAM_SIZE-1) -#define ARAM_MASK (ARAM_SIZE-1) -#define BIOS_MASK (BIOS_SIZE-1) - -#ifdef FLASH_SIZE -#define FLASH_MASK (FLASH_SIZE-1) -#endif - -#ifdef BBSRAM_SIZE -#define BBSRAM_MASK (BBSRAM_SIZE-1) -#endif - -#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs - -#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs -#define ADAC_CLOCK (AICA_CORE_CLOCK/2) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs -#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM -#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM -#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200) -#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip -#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls - - enum ndc_error_codes { rv_ok = 0, //no error