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sh4: only reset serial pipe on hard reset 

See d3690b12c6
This commit is contained in:
Flyinghead 2023-04-09 20:56:14 +02:00
parent e327172fd0
commit b556617e1d
3 changed files with 6 additions and 5 deletions
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2
core/hw/sh4/modules/modules.h
View File

@ -88,7 +88,7 @@ class SCIFRegisters : public RegisterBank<SCIF, 10>
public:
void init();
void reset();
void reset(bool hard);
void term();
};
extern SCIFRegisters scif;

7
core/hw/sh4/modules/serial.cpp
View File

@ -260,7 +260,7 @@ void SCIFRegisters::init()
//SCIF SCLSR2 0xFFE80024 0x1FE80024 16 0x0000 0x0000 Held Held Pclk
setRW<SCIF_SCLSR2_addr, u16, 1>();
reset();
reset(true);
}
void SCIRegisters::init()
@ -279,7 +279,7 @@ void SCIRegisters::init()
reset();
}
void SCIFRegisters::reset()
void SCIFRegisters::reset(bool hard)
{
super::reset();
@ -298,7 +298,8 @@ void SCIFRegisters::reset()
SCIF_SCBRR2 = 0xFF;
SCIF_SCFSR2.full = 0x060;
ptyPipe.init();
if (hard)
ptyPipe.init();
}
void SCIRegisters::reset()

2
core/hw/sh4/sh4_mmr.cpp
View File

@ -605,7 +605,7 @@ void sh4_mmr_reset(bool hard)
dmac.reset();
intc.reset();
rtc.reset();
scif.reset();
scif.reset(hard);
sci.reset();
tmu.reset();
ubc.reset();