From b556617e1d8b7750f72f81796ec1a1d53da72e70 Mon Sep 17 00:00:00 2001
From: Flyinghead <raphael.jean@gmail.com>
Date: Sun, 9 Apr 2023 20:56:14 +0200
Subject: [PATCH] sh4: only reset serial pipe on hard reset

See d3690b12c6ec6cf82e59266326a4031f0d20f477
---
 core/hw/sh4/modules/modules.h  | 2 +-
 core/hw/sh4/modules/serial.cpp | 7 ++++---
 core/hw/sh4/sh4_mmr.cpp        | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/core/hw/sh4/modules/modules.h b/core/hw/sh4/modules/modules.h
index 88da8ee2b..a700f8936 100644
--- a/core/hw/sh4/modules/modules.h
+++ b/core/hw/sh4/modules/modules.h
@@ -88,7 +88,7 @@ class SCIFRegisters : public RegisterBank<SCIF, 10>
 
 public:
 	void init();
-	void reset();
+	void reset(bool hard);
 	void term();
 };
 extern SCIFRegisters scif;
diff --git a/core/hw/sh4/modules/serial.cpp b/core/hw/sh4/modules/serial.cpp
index c1b0e3589..df6b5bd58 100644
--- a/core/hw/sh4/modules/serial.cpp
+++ b/core/hw/sh4/modules/serial.cpp
@@ -260,7 +260,7 @@ void SCIFRegisters::init()
 	//SCIF SCLSR2 0xFFE80024 0x1FE80024 16 0x0000 0x0000 Held Held Pclk
 	setRW<SCIF_SCLSR2_addr, u16, 1>();
 
-	reset();
+	reset(true);
 }
 
 void SCIRegisters::init()
@@ -279,7 +279,7 @@ void SCIRegisters::init()
 	reset();
 }
 
-void SCIFRegisters::reset()
+void SCIFRegisters::reset(bool hard)
 {
 	super::reset();
 
@@ -298,7 +298,8 @@ void SCIFRegisters::reset()
 	SCIF_SCBRR2 = 0xFF;
 	SCIF_SCFSR2.full = 0x060;
 
-	ptyPipe.init();
+	if (hard)
+		ptyPipe.init();
 }
 
 void SCIRegisters::reset()
diff --git a/core/hw/sh4/sh4_mmr.cpp b/core/hw/sh4/sh4_mmr.cpp
index 58b2962ef..c584b24b8 100644
--- a/core/hw/sh4/sh4_mmr.cpp
+++ b/core/hw/sh4/sh4_mmr.cpp
@@ -605,7 +605,7 @@ void sh4_mmr_reset(bool hard)
 	dmac.reset();
 	intc.reset();
 	rtc.reset();
-	scif.reset();
+	scif.reset(hard);
 	sci.reset();
 	tmu.reset();
 	ubc.reset();