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Replace DECL_ALIGN macros by alignas

This commit is contained in:
scribam 2020-02-19 23:20:32 +01:00
parent 21f1517a5f
commit 53bde38035
11 changed files with 25 additions and 29 deletions
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2
core/hw/aica/dsp.cpp
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@ -20,7 +20,7 @@
See LICENSE & COPYRIGHT files further details
*/
DECL_ALIGN(4096) dsp_t dsp;
alignas(4096) dsp_t dsp;
//float format is ?
u16 DYNACALL PACK(s32 val)

3
core/hw/aica/dsp.h
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@ -85,8 +85,7 @@ struct dsp_t
bool dyndirty;
};
DECL_ALIGN(4096)
extern dsp_t dsp;
alignas(4096) extern dsp_t dsp;
void dsp_init();
void dsp_term();

2
core/hw/aica/dsp_x64.cpp
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@ -30,7 +30,7 @@
#define CC_RW2RX(ptr) (ptr)
#define CC_RX2RW(ptr) (ptr)
DECL_ALIGN(4096) static u8 CodeBuffer[32 * 1024]
alignas(4096) static u8 CodeBuffer[32 * 1024]
#if defined(_WIN32)
;
#elif HOST_OS == OS_LINUX

2
core/hw/arm7/arm7.cpp
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@ -30,7 +30,7 @@
//bool arm_FiqPending; -- not used , i use the input directly :)
//bool arm_IrqPending;
DECL_ALIGN(8) reg_pair arm_Reg[RN_ARM_REG_COUNT];
alignas(8) reg_pair arm_Reg[RN_ARM_REG_COUNT];
void CPUSwap(u32 *a, u32 *b)
{

6
core/hw/pvr/ta.cpp
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@ -16,18 +16,18 @@ extern u32 ta_type_lut[256];
#include <xmmintrin.h>
struct simd256_t
{
DECL_ALIGN(32) __m128 data[2];
alignas(32) __m128 data[2];
};
#elif HOST_CPU == CPU_ARM && defined(__ARM_NEON__)
#include <arm_neon.h>
struct simd256_t
{
DECL_ALIGN(32) uint64x2_t data[2];
alignas(32) uint64x2_t data[2];
};
#else
struct simd256_t
{
DECL_ALIGN(32) u64 data[4];
alignas(32) u64 data[4];
};
#endif

12
core/hw/pvr/ta_vtx.cpp
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@ -62,12 +62,12 @@ static PolyParam* CurrentPP;
static List<PolyParam>* CurrentPPlist;
//TA state vars
DECL_ALIGN(4) static u8 FaceBaseColor[4];
DECL_ALIGN(4) static u8 FaceOffsColor[4];
DECL_ALIGN(4) static u8 FaceBaseColor1[4];
DECL_ALIGN(4) static u8 FaceOffsColor1[4];
DECL_ALIGN(4) static u32 SFaceBaseColor;
DECL_ALIGN(4) static u32 SFaceOffsColor;
alignas(4) static u8 FaceBaseColor[4];
alignas(4) static u8 FaceOffsColor[4];
alignas(4) static u8 FaceBaseColor1[4];
alignas(4) static u8 FaceOffsColor1[4];
alignas(4) static u32 SFaceBaseColor;
alignas(4) static u32 SFaceOffsColor;
//misc ones
static const u32 ListType_None = -1;

6
core/hw/sh4/sh4_interrupts.cpp
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@ -42,11 +42,11 @@ struct InterptSourceList_Entry
InterptSourceList_Entry InterruptSourceList[28];
//Maps siid -> EventID
DECL_ALIGN(64) u16 InterruptEnvId[32] = { 0 };
alignas(64) u16 InterruptEnvId[32] = { 0 };
//Maps piid -> 1<<siid
DECL_ALIGN(64) u32 InterruptBit[32] = { 0 };
alignas(64) u32 InterruptBit[32] = { 0 };
//Maps sh4 interrupt level to inclusive bitfield
DECL_ALIGN(64) u32 InterruptLevelBit[16] = { 0 };
alignas(64) u32 InterruptLevelBit[16] = { 0 };
bool Do_Interrupt(u32 intEvn);
bool Do_Exception(u32 epc, u32 expEvn, u32 CallVect);

2
core/rec-x86/rec_x86_driver.cpp
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@ -76,7 +76,7 @@ u32 csc_sidx=1;
x86_reg alloc_regs[]={EBX,EBP,ESI,EDI,NO_REG};
x86_reg xmm_alloc_regs[]={XMM7,XMM6,XMM5,XMM4,NO_REG};
f32 DECL_ALIGN(16) thaw_regs[4];
alignas(16) f32 thaw_regs[4];
void x86_reg_alloc::Preload(u32 reg,x86_reg nreg)

4
core/rec-x86/rec_x86_il.cpp
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@ -928,7 +928,7 @@ void ngen_opcode(RuntimeBlockInfo* block, shil_opcode* op,x86_block* x86e, bool
verify(reg.IsAllocf(op->rs1));
verify(reg.IsAllocf(op->rd));
static DECL_ALIGN(16) u32 AND_ABS_MASK[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
alignas(16) static u32 AND_ABS_MASK[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF };
if (op->rd._reg != op->rs1._reg)
x86e->Emit(op_movss, reg.mapf(op->rd), reg.mapf(op->rs1));
@ -941,7 +941,7 @@ void ngen_opcode(RuntimeBlockInfo* block, shil_opcode* op,x86_block* x86e, bool
verify(reg.IsAllocf(op->rs1));
verify(reg.IsAllocf(op->rd));
static DECL_ALIGN(16) u32 XOR_NEG_MASK[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
alignas(16) static u32 XOR_NEG_MASK[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
if (op->rd._reg != op->rs1._reg)
x86e->Emit(op_movss, reg.mapf(op->rd), reg.mapf(op->rs1));

10
core/serialize.cpp
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@ -38,14 +38,14 @@ extern u32 e68k_reg_L;
extern u32 e68k_reg_M;
//./core/hw/arm7/arm7.cpp
extern DECL_ALIGN(8) reg_pair arm_Reg[RN_ARM_REG_COUNT];
alignas(8) extern reg_pair arm_Reg[RN_ARM_REG_COUNT];
extern bool armIrqEnable;
extern bool armFiqEnable;
extern int armMode;
extern bool Arm7Enabled;
//./core/hw/aica/dsp.o
extern DECL_ALIGN(4096) dsp_t dsp;
alignas(4096) extern dsp_t dsp;
extern AicaTimer timers[3];
@ -157,9 +157,9 @@ extern std::array<u8, OnChipRAM_SIZE> OnChipRAM;
extern VArray2 mem_b;
//./core/hw/sh4/sh4_interrupts.o
extern DECL_ALIGN(64) u16 InterruptEnvId[32];
extern DECL_ALIGN(64) u32 InterruptBit[32];
extern DECL_ALIGN(64) u32 InterruptLevelBit[16];
alignas(64) extern u16 InterruptEnvId[32];
alignas(64) extern u32 InterruptBit[32];
alignas(64) extern u32 InterruptLevelBit[16];
extern u32 interrupt_vpend; // Vector of pending interrupts
extern u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts)
extern u32 decoded_srimask; // Vector of interrupts allowed by SR.IMSK (-1 inhibits all interrupts)

5
core/types.h
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@ -2,13 +2,10 @@
#include "build.h"
#ifdef _MSC_VER
#define DECL_ALIGN(x) __declspec(align(x))
#else
#ifndef _MSC_VER
#ifndef __forceinline
#define __forceinline inline
#endif
#define DECL_ALIGN(x) __attribute__((aligned(x)))
#ifndef _WIN32
#define __debugbreak
#endif