From 53bde380358c37950cb7b5b753e82425964778ce Mon Sep 17 00:00:00 2001 From: scribam Date: Wed, 19 Feb 2020 23:20:32 +0100 Subject: [PATCH] Replace DECL_ALIGN macros by alignas --- core/hw/aica/dsp.cpp | 2 +- core/hw/aica/dsp.h | 3 +-- core/hw/aica/dsp_x64.cpp | 2 +- core/hw/arm7/arm7.cpp | 2 +- core/hw/pvr/ta.cpp | 6 +++--- core/hw/pvr/ta_vtx.cpp | 12 ++++++------ core/hw/sh4/sh4_interrupts.cpp | 6 +++--- core/rec-x86/rec_x86_driver.cpp | 2 +- core/rec-x86/rec_x86_il.cpp | 4 ++-- core/serialize.cpp | 10 +++++----- core/types.h | 5 +---- 11 files changed, 25 insertions(+), 29 deletions(-) diff --git a/core/hw/aica/dsp.cpp b/core/hw/aica/dsp.cpp index 80ba419e7..fc1182f98 100644 --- a/core/hw/aica/dsp.cpp +++ b/core/hw/aica/dsp.cpp @@ -20,7 +20,7 @@ See LICENSE & COPYRIGHT files further details */ -DECL_ALIGN(4096) dsp_t dsp; +alignas(4096) dsp_t dsp; //float format is ? u16 DYNACALL PACK(s32 val) diff --git a/core/hw/aica/dsp.h b/core/hw/aica/dsp.h index 6d5b76c91..cb5a805d5 100644 --- a/core/hw/aica/dsp.h +++ b/core/hw/aica/dsp.h @@ -85,8 +85,7 @@ struct dsp_t bool dyndirty; }; -DECL_ALIGN(4096) -extern dsp_t dsp; +alignas(4096) extern dsp_t dsp; void dsp_init(); void dsp_term(); diff --git a/core/hw/aica/dsp_x64.cpp b/core/hw/aica/dsp_x64.cpp index 17dec9d6e..b8fc963b7 100644 --- a/core/hw/aica/dsp_x64.cpp +++ b/core/hw/aica/dsp_x64.cpp @@ -30,7 +30,7 @@ #define CC_RW2RX(ptr) (ptr) #define CC_RX2RW(ptr) (ptr) -DECL_ALIGN(4096) static u8 CodeBuffer[32 * 1024] +alignas(4096) static u8 CodeBuffer[32 * 1024] #if defined(_WIN32) ; #elif HOST_OS == OS_LINUX diff --git a/core/hw/arm7/arm7.cpp b/core/hw/arm7/arm7.cpp index f8332a083..820e318ec 100644 --- a/core/hw/arm7/arm7.cpp +++ b/core/hw/arm7/arm7.cpp @@ -30,7 +30,7 @@ //bool arm_FiqPending; -- not used , i use the input directly :) //bool arm_IrqPending; -DECL_ALIGN(8) reg_pair arm_Reg[RN_ARM_REG_COUNT]; +alignas(8) reg_pair arm_Reg[RN_ARM_REG_COUNT]; void CPUSwap(u32 *a, u32 *b) { diff --git a/core/hw/pvr/ta.cpp b/core/hw/pvr/ta.cpp index 2e06d772d..16db412d5 100644 --- a/core/hw/pvr/ta.cpp +++ b/core/hw/pvr/ta.cpp @@ -16,18 +16,18 @@ extern u32 ta_type_lut[256]; #include struct simd256_t { - DECL_ALIGN(32) __m128 data[2]; + alignas(32) __m128 data[2]; }; #elif HOST_CPU == CPU_ARM && defined(__ARM_NEON__) #include struct simd256_t { - DECL_ALIGN(32) uint64x2_t data[2]; + alignas(32) uint64x2_t data[2]; }; #else struct simd256_t { -DECL_ALIGN(32) u64 data[4]; + alignas(32) u64 data[4]; }; #endif diff --git a/core/hw/pvr/ta_vtx.cpp b/core/hw/pvr/ta_vtx.cpp index ce629df17..5ce3a34d5 100644 --- a/core/hw/pvr/ta_vtx.cpp +++ b/core/hw/pvr/ta_vtx.cpp @@ -62,12 +62,12 @@ static PolyParam* CurrentPP; static List* CurrentPPlist; //TA state vars -DECL_ALIGN(4) static u8 FaceBaseColor[4]; -DECL_ALIGN(4) static u8 FaceOffsColor[4]; -DECL_ALIGN(4) static u8 FaceBaseColor1[4]; -DECL_ALIGN(4) static u8 FaceOffsColor1[4]; -DECL_ALIGN(4) static u32 SFaceBaseColor; -DECL_ALIGN(4) static u32 SFaceOffsColor; +alignas(4) static u8 FaceBaseColor[4]; +alignas(4) static u8 FaceOffsColor[4]; +alignas(4) static u8 FaceBaseColor1[4]; +alignas(4) static u8 FaceOffsColor1[4]; +alignas(4) static u32 SFaceBaseColor; +alignas(4) static u32 SFaceOffsColor; //misc ones static const u32 ListType_None = -1; diff --git a/core/hw/sh4/sh4_interrupts.cpp b/core/hw/sh4/sh4_interrupts.cpp index cefbacb32..777fb6113 100644 --- a/core/hw/sh4/sh4_interrupts.cpp +++ b/core/hw/sh4/sh4_interrupts.cpp @@ -42,11 +42,11 @@ struct InterptSourceList_Entry InterptSourceList_Entry InterruptSourceList[28]; //Maps siid -> EventID -DECL_ALIGN(64) u16 InterruptEnvId[32] = { 0 }; +alignas(64) u16 InterruptEnvId[32] = { 0 }; //Maps piid -> 1<rs1)); verify(reg.IsAllocf(op->rd)); - static DECL_ALIGN(16) u32 AND_ABS_MASK[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF }; + alignas(16) static u32 AND_ABS_MASK[4] = { 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF }; if (op->rd._reg != op->rs1._reg) x86e->Emit(op_movss, reg.mapf(op->rd), reg.mapf(op->rs1)); @@ -941,7 +941,7 @@ void ngen_opcode(RuntimeBlockInfo* block, shil_opcode* op,x86_block* x86e, bool verify(reg.IsAllocf(op->rs1)); verify(reg.IsAllocf(op->rd)); - static DECL_ALIGN(16) u32 XOR_NEG_MASK[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 }; + alignas(16) static u32 XOR_NEG_MASK[4] = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 }; if (op->rd._reg != op->rs1._reg) x86e->Emit(op_movss, reg.mapf(op->rd), reg.mapf(op->rs1)); diff --git a/core/serialize.cpp b/core/serialize.cpp index 6bedf1d5c..71df76401 100644 --- a/core/serialize.cpp +++ b/core/serialize.cpp @@ -38,14 +38,14 @@ extern u32 e68k_reg_L; extern u32 e68k_reg_M; //./core/hw/arm7/arm7.cpp -extern DECL_ALIGN(8) reg_pair arm_Reg[RN_ARM_REG_COUNT]; +alignas(8) extern reg_pair arm_Reg[RN_ARM_REG_COUNT]; extern bool armIrqEnable; extern bool armFiqEnable; extern int armMode; extern bool Arm7Enabled; //./core/hw/aica/dsp.o -extern DECL_ALIGN(4096) dsp_t dsp; +alignas(4096) extern dsp_t dsp; extern AicaTimer timers[3]; @@ -157,9 +157,9 @@ extern std::array OnChipRAM; extern VArray2 mem_b; //./core/hw/sh4/sh4_interrupts.o -extern DECL_ALIGN(64) u16 InterruptEnvId[32]; -extern DECL_ALIGN(64) u32 InterruptBit[32]; -extern DECL_ALIGN(64) u32 InterruptLevelBit[16]; +alignas(64) extern u16 InterruptEnvId[32]; +alignas(64) extern u32 InterruptBit[32]; +alignas(64) extern u32 InterruptLevelBit[16]; extern u32 interrupt_vpend; // Vector of pending interrupts extern u32 interrupt_vmask; // Vector of masked interrupts (-1 inhibits all interrupts) extern u32 decoded_srimask; // Vector of interrupts allowed by SR.IMSK (-1 inhibits all interrupts) diff --git a/core/types.h b/core/types.h index c902e16f6..ebce054a3 100644 --- a/core/types.h +++ b/core/types.h @@ -2,13 +2,10 @@ #include "build.h" -#ifdef _MSC_VER -#define DECL_ALIGN(x) __declspec(align(x)) -#else +#ifndef _MSC_VER #ifndef __forceinline #define __forceinline inline #endif -#define DECL_ALIGN(x) __attribute__((aligned(x))) #ifndef _WIN32 #define __debugbreak #endif