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Add TA_GLOB_TILE_CLIP struct. Fix typo.

This commit is contained in:
Flyinghead 2018-05-23 12:05:58 +02:00
parent bccfb5b70c
commit 488b9ab831
2 changed files with 16 additions and 4 deletions
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18
core/hw/pvr/pvr_regs.h
View File

@ -354,7 +354,19 @@ union FPU_SHAD_SCALE_type
struct
{
u32 scale_factor : 8;
u32 intesity_shadow : 1;
u32 intensity_shadow : 1;
};
u32 full;
};
union TA_GLOB_TILE_CLIP_type
{
struct
{
u32 tile_x_num : 6;
u32 reserved : 10;
u32 tile_y_num : 4;
u32 reserved2 : 12;
};
u32 full;
};
@ -467,7 +479,7 @@ union FPU_SHAD_SCALE_type
#define TA_ISP_LIMIT PvrReg(TA_ISP_LIMIT_addr,u32) // RW Current ISP/TSP Parameter write address
#define TA_NEXT_OPB PvrReg(TA_NEXT_OPB_addr,u32) // R Global Tile clip control
#define TA_ITP_CURRENT PvrReg(TA_ITP_CURRENT_addr,u32) // R Current ISP/TSP Parameter write address
#define TA_GLOB_TILE_CLIP PvrReg(TA_GLOB_TILE_CLIP_addr,u32) // RW Global Tile clip control
#define TA_GLOB_TILE_CLIP PvrReg(TA_GLOB_TILE_CLIP_addr, TA_GLOB_TILE_CLIP_type) // RW Global Tile clip control
#define TA_ALLOC_CTRL PvrReg(TA_ALLOC_CTRL_addr,u32) // RW Object list control
#define TA_LIST_INIT PvrReg(TA_LIST_INIT_addr,u32) // RW TA initialization
#define TA_YUV_TEX_BASE PvrReg(TA_YUV_TEX_BASE_addr,u32) // RW YUV422 texture write start address
@ -484,4 +496,4 @@ union FPU_SHAD_SCALE_type
#define TA_CURRENT_CTX (TA_ISP_BASE & 0xF00000)
#define CORE_CURRENT_CTX (PARAM_BASE & 0xF00000)
#define CORE_CURRENT_CTX (PARAM_BASE & 0xF00000)

2
core/hw/pvr/ta_vtx.cpp
View File

@ -1575,7 +1575,7 @@ void FillBGP(TA_context* ctx)
PolyParam* bgpp=ctx->rend.global_param_op.head();
Vertex* cv=ctx->rend.verts.head();
bool PSVM=FPU_SHAD_SCALE.intesity_shadow!=0; //double parameters for volumes
bool PSVM=FPU_SHAD_SCALE.intensity_shadow!=0; //double parameters for volumes
//Get the strip base
u32 strip_base=(param_base + ISP_BACKGND_T.tag_address*4); //this is *not* VRAM_MASK on purpose.It fixes naomi bios and quite a few naomi games