From 488b9ab831a4f87e91faf1d469a41a4c617ed58b Mon Sep 17 00:00:00 2001 From: Flyinghead Date: Wed, 23 May 2018 12:05:58 +0200 Subject: [PATCH] Add TA_GLOB_TILE_CLIP struct. Fix typo. --- core/hw/pvr/pvr_regs.h | 18 +++++++++++++++--- core/hw/pvr/ta_vtx.cpp | 2 +- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/core/hw/pvr/pvr_regs.h b/core/hw/pvr/pvr_regs.h index 4fe0f8f17..93969c8bc 100644 --- a/core/hw/pvr/pvr_regs.h +++ b/core/hw/pvr/pvr_regs.h @@ -354,7 +354,19 @@ union FPU_SHAD_SCALE_type struct { u32 scale_factor : 8; - u32 intesity_shadow : 1; + u32 intensity_shadow : 1; + }; + u32 full; +}; + +union TA_GLOB_TILE_CLIP_type +{ + struct + { + u32 tile_x_num : 6; + u32 reserved : 10; + u32 tile_y_num : 4; + u32 reserved2 : 12; }; u32 full; }; @@ -467,7 +479,7 @@ union FPU_SHAD_SCALE_type #define TA_ISP_LIMIT PvrReg(TA_ISP_LIMIT_addr,u32) // RW Current ISP/TSP Parameter write address #define TA_NEXT_OPB PvrReg(TA_NEXT_OPB_addr,u32) // R Global Tile clip control #define TA_ITP_CURRENT PvrReg(TA_ITP_CURRENT_addr,u32) // R Current ISP/TSP Parameter write address -#define TA_GLOB_TILE_CLIP PvrReg(TA_GLOB_TILE_CLIP_addr,u32) // RW Global Tile clip control +#define TA_GLOB_TILE_CLIP PvrReg(TA_GLOB_TILE_CLIP_addr, TA_GLOB_TILE_CLIP_type) // RW Global Tile clip control #define TA_ALLOC_CTRL PvrReg(TA_ALLOC_CTRL_addr,u32) // RW Object list control #define TA_LIST_INIT PvrReg(TA_LIST_INIT_addr,u32) // RW TA initialization #define TA_YUV_TEX_BASE PvrReg(TA_YUV_TEX_BASE_addr,u32) // RW YUV422 texture write start address @@ -484,4 +496,4 @@ union FPU_SHAD_SCALE_type #define TA_CURRENT_CTX (TA_ISP_BASE & 0xF00000) -#define CORE_CURRENT_CTX (PARAM_BASE & 0xF00000) \ No newline at end of file +#define CORE_CURRENT_CTX (PARAM_BASE & 0xF00000) diff --git a/core/hw/pvr/ta_vtx.cpp b/core/hw/pvr/ta_vtx.cpp index 4304c87c1..ce67dd956 100644 --- a/core/hw/pvr/ta_vtx.cpp +++ b/core/hw/pvr/ta_vtx.cpp @@ -1575,7 +1575,7 @@ void FillBGP(TA_context* ctx) PolyParam* bgpp=ctx->rend.global_param_op.head(); Vertex* cv=ctx->rend.verts.head(); - bool PSVM=FPU_SHAD_SCALE.intesity_shadow!=0; //double parameters for volumes + bool PSVM=FPU_SHAD_SCALE.intensity_shadow!=0; //double parameters for volumes //Get the strip base u32 strip_base=(param_base + ISP_BACKGND_T.tag_address*4); //this is *not* VRAM_MASK on purpose.It fixes naomi bios and quite a few naomi games