replace Array with std::array
This commit is contained in:
Flyinghead
parent
12193f9510
commit
0d9214df40
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@ -16,7 +16,7 @@
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extern void dc_request_reset();
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Array<RegisterStruct> sb_regs(0x540);
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std::array<RegisterStruct, 0x540> sb_regs;
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//(addr>= 0x005F6800) && (addr<=0x005F7CFF) -> 0x1500 bytes -> 0x540 possible registers , 125 actually exist only
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// System Control Reg. //0x100 bytes
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@ -127,9 +127,9 @@ void sb_rio_register(u32 reg_addr, RegIO flags, RegReadAddrFP* rf, RegWriteAddrF
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{
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u32 idx=(reg_addr-SB_BASE)/4;
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verify(idx<sb_regs.Size);
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verify(idx < sb_regs.size());
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sb_regs[idx].flags = flags | REG_ACCESS_32;
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sb_regs[idx].flags = flags;
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if (flags == RIO_NO_ACCESS)
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{
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@ -180,12 +180,8 @@ void SB_SFRES_write32(u32 addr, u32 data)
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}
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void sb_Init()
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{
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sb_regs.Zero();
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for (u32 i=0;i<sb_regs.Size;i++)
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{
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sb_rio_register(SB_BASE+i*4,RIO_NO_ACCESS);
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}
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for (u32 i = 0; i < sb_regs.size(); i++)
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sb_rio_register(SB_BASE + i * 4, RIO_NO_ACCESS);
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//0x005F6800 SB_C2DSTAT RW ch2-DMA destination address
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sb_rio_register(SB_C2DSTAT_addr,RIO_DATA);
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@ -612,8 +608,8 @@ void sb_Reset(bool hard)
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{
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if (hard)
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{
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for (u32 i = 0; i < sb_regs.Size; i++)
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sb_regs[i].reset();
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for (auto& reg : sb_regs)
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reg.reset();
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}
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SB_ISTNRM = 0;
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SB_FFST_rc = 0;
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@ -3,6 +3,7 @@
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*/
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#pragma once
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#include <array>
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#include "types.h"
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@ -13,7 +14,7 @@ void sb_Init();
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void sb_Reset(bool hard);
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void sb_Term();
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extern Array<RegisterStruct> sb_regs;
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extern std::array<RegisterStruct, 0x540> sb_regs;
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#define SB_BASE 0x005F6800
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@ -314,7 +315,7 @@ extern Array<RegisterStruct> sb_regs;
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//0x005F7CF8 SB_PDLEND R PVR-DMA transfer counter
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#define SB_PDLEND_addr 0x005F7CF8
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#define SB_REGN_32(addr) (sb_regs[(addr-SB_BASE)/4].data32)
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#define SB_REGN_32(addr) (sb_regs[((addr) - SB_BASE) / 4].data32)
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#define SB_REG_32(name) SB_REGN_32(SB_##name##_addr)
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#define SB_REG_T(name) ((SB_name##_t&)SB_REG_T(name))
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@ -1,6 +1,7 @@
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/*
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Sh4 internal register routing (P4 & 'area 7')
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*/
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#include <array>
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#include "types.h"
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#include "sh4_mmr.h"
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@ -11,45 +12,44 @@
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//64bytes of sq // now on context ~
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Array<u8> OnChipRAM;
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std::array<u8, OnChipRAM_SIZE> OnChipRAM;
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//All registers are 4 byte aligned
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Array<RegisterStruct> CCN(18,true); //CCN : 16 registers
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Array<RegisterStruct> UBC(9,true); //UBC : 9 registers
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Array<RegisterStruct> BSC(19,true); //BSC : 18 registers
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Array<RegisterStruct> DMAC(17,true); //DMAC : 17 registers
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Array<RegisterStruct> CPG(5,true); //CPG : 5 registers
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Array<RegisterStruct> RTC(16,true); //RTC : 16 registers
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Array<RegisterStruct> INTC(5,true); //INTC : 5 registers
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Array<RegisterStruct> TMU(12,true); //TMU : 12 registers
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Array<RegisterStruct> SCI(8,true); //SCI : 8 registers
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Array<RegisterStruct> SCIF(10,true); //SCIF : 10 registers
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std::array<RegisterStruct, 18> CCN;
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std::array<RegisterStruct, 9> UBC;
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std::array<RegisterStruct, 19> BSC;
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std::array<RegisterStruct, 17> DMAC;
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std::array<RegisterStruct, 5> CPG;
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std::array<RegisterStruct, 16> RTC;
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std::array<RegisterStruct, 5> INTC;
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std::array<RegisterStruct, 12> TMU;
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std::array<RegisterStruct, 8> SCI;
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std::array<RegisterStruct, 10> SCIF;
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Array<RegisterStruct> * const AllRegisters[] = { &CCN, &UBC, &BSC, &DMAC, &CPG, &RTC, &INTC, &TMU, &SCI, &SCIF };
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u32 sh4io_read_noacc(u32 addr)
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static u32 sh4io_read_noacc(u32 addr)
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{
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INFO_LOG(SH4, "sh4io: Invalid read access @@ %08X", addr);
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return 0;
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}
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void sh4io_write_noacc(u32 addr, u32 data)
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static void sh4io_write_noacc(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Invalid write access @@ %08X %08X", addr, data);
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//verify(false);
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}
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void sh4io_write_const(u32 addr, u32 data)
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static void sh4io_write_const(u32 addr, u32 data)
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{
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INFO_LOG(SH4, "sh4io: Const write ignored @@ %08X <- %08X", addr, data);
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}
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void sh4_rio_reg(Array<RegisterStruct>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf)
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template<class T>
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void sh4_rio_reg(T& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf)
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{
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u32 idx=(addr&255)/4;
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verify(idx<arr.Size);
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verify(idx < arr.size());
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arr[idx].flags = flags | REG_ACCESS_32;
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arr[idx].flags = flags;
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if (flags == RIO_NO_ACCESS)
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{
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@ -71,9 +71,18 @@ void sh4_rio_reg(Array<RegisterStruct>& arr, u32 addr, RegIO flags, u32 sz, RegR
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arr[idx].writeFunctionAddr=wf==0?&sh4io_write_noacc:wf;
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}
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}
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template void sh4_rio_reg(std::array<RegisterStruct, 5>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 8>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 9>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 10>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 12>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 16>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 17>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 18>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template void sh4_rio_reg(std::array<RegisterStruct, 19>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf);
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template<u32 sz>
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u32 sh4_rio_read(Array<RegisterStruct>& sb_regs, u32 addr)
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template<u32 sz, class T>
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u32 sh4_rio_read(T& regs, u32 addr)
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{
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u32 offset = addr&255;
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#ifdef TRACE
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@ -86,21 +95,21 @@ u32 sh4_rio_read(Array<RegisterStruct>& sb_regs, u32 addr)
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offset>>=2;
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#ifdef TRACE
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if (sb_regs[offset].flags & sz)
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if (regs[offset].flags & sz)
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{
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#endif
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if (!(sb_regs[offset].flags & REG_RF) )
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if (!(regs[offset].flags & REG_RF) )
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{
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if (sz==4)
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return sb_regs[offset].data32;
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return regs[offset].data32;
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else if (sz==2)
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return sb_regs[offset].data16;
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return regs[offset].data16;
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else
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return sb_regs[offset].data8;
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return regs[offset].data8;
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}
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else
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{
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return sb_regs[offset].readFunctionAddr(addr);
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return regs[offset].readFunctionAddr(addr);
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}
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#ifdef TRACE
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}
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@ -112,8 +121,8 @@ u32 sh4_rio_read(Array<RegisterStruct>& sb_regs, u32 addr)
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return 0;
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}
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template<u32 sz>
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void sh4_rio_write(Array<RegisterStruct>& sb_regs, u32 addr, u32 data)
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template<u32 sz, class T>
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void sh4_rio_write(T& regs, u32 addr, u32 data)
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{
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u32 offset = addr&255;
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#ifdef TRACE
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@ -124,23 +133,23 @@ void sh4_rio_write(Array<RegisterStruct>& sb_regs, u32 addr, u32 data)
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#endif
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offset>>=2;
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#ifdef TRACE
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if (sb_regs[offset].flags & sz)
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if (regs[offset].flags & sz)
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{
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#endif
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if (!(sb_regs[offset].flags & REG_WF) )
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if (!(regs[offset].flags & REG_WF) )
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{
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if (sz==4)
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sb_regs[offset].data32=data;
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regs[offset].data32=data;
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else if (sz==2)
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sb_regs[offset].data16=(u16)data;
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regs[offset].data16=(u16)data;
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else
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sb_regs[offset].data8=(u8)data;
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regs[offset].data8=(u8)data;
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return;
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}
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else
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{
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//printf("RSW: %08X\n",addr);
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sb_regs[offset].writeFunctionAddr(addr,data);
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regs[offset].writeFunctionAddr(addr,data);
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return;
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}
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#ifdef TRACE
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@ -794,25 +803,30 @@ void DYNACALL WriteMem_area7_OCR_T(u32 addr,T data)
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}
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}
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template <class T>
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static void init_regs(T& regs)
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{
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for (auto& reg : regs)
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{
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reg.flags = RIO_NO_ACCESS;
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reg.readFunctionAddr = &sh4io_read_noacc;
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reg.writeFunctionAddr = &sh4io_write_noacc;
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}
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}
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//Init/Res/Term
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void sh4_mmr_init()
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{
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OnChipRAM.Resize(OnChipRAM_SIZE,false);
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for (u32 i=0;i<30;i++)
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{
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if (i<CCN.Size) sh4_rio_reg(CCN,CCN_BASE_addr+i*4,RIO_NO_ACCESS,32); //(16,true); //CCN : 14 registers
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if (i<UBC.Size) sh4_rio_reg(UBC,UBC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(9,true); //UBC : 9 registers
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if (i<BSC.Size) sh4_rio_reg(BSC,BSC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(19,true); //BSC : 18 registers
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if (i<DMAC.Size) sh4_rio_reg(DMAC,DMAC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(17,true); //DMAC : 17 registers
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if (i<CPG.Size) sh4_rio_reg(CPG,CPG_BASE_addr+i*4,RIO_NO_ACCESS,32); //(5,true); //CPG : 5 registers
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if (i<RTC.Size) sh4_rio_reg(RTC,RTC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(16,true); //RTC : 16 registers
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if (i<INTC.Size) sh4_rio_reg(INTC,INTC_BASE_addr+i*4,RIO_NO_ACCESS,32); //(4,true); //INTC : 4 registers
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if (i<TMU.Size) sh4_rio_reg(TMU,TMU_BASE_addr+i*4,RIO_NO_ACCESS,32); //(12,true); //TMU : 12 registers
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if (i<SCI.Size) sh4_rio_reg(SCI,SCI_BASE_addr+i*4,RIO_NO_ACCESS,32); //(8,true); //SCI : 8 registers
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if (i<SCIF.Size) sh4_rio_reg(SCIF,SCIF_BASE_addr+i*4,RIO_NO_ACCESS,32); //(10,true); //SCIF : 10 registers
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}
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init_regs(CCN);
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init_regs(UBC);
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init_regs(BSC);
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init_regs(DMAC);
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init_regs(CPG);
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init_regs(RTC);
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init_regs(INTC);
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init_regs(TMU);
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init_regs(SCI);
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init_regs(SCIF);
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//initialise Register structs
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bsc_init();
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@ -830,11 +844,28 @@ void sh4_mmr_reset(bool hard)
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{
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if (hard)
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{
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for (int i = 0; i < ARRAY_SIZE(AllRegisters); i++)
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for (int j = 0; j < AllRegisters[i]->Size; j++)
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(*AllRegisters[i])[j].reset();
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for (auto& reg : CCN)
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reg.reset();
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for (auto& reg : UBC)
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reg.reset();
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for (auto& reg : BSC)
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reg.reset();
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for (auto& reg : DMAC)
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reg.reset();
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for (auto& reg : CPG)
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reg.reset();
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for (auto& reg : RTC)
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reg.reset();
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for (auto& reg : INTC)
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reg.reset();
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for (auto& reg : TMU)
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reg.reset();
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for (auto& reg : SCI)
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reg.reset();
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for (auto& reg : SCIF)
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reg.reset();
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}
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OnChipRAM.Zero();
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OnChipRAM = {};
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//Reset register values
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bsc_reset(hard);
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ccn_reset();
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@ -859,7 +890,6 @@ void sh4_mmr_term()
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cpg_term();
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ccn_term();
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bsc_term();
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OnChipRAM.Free();
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}
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//Mem map :)
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@ -1,4 +1,5 @@
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#pragma once
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#include <array>
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#include "types.h"
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#include "../sh4/sh4_if.h"
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@ -12,16 +13,16 @@ void map_p4();
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#define sq_both ((u8*)sh4rcb.sq_buffer)
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extern Array<RegisterStruct> CCN; //CCN : 14 registers
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extern Array<RegisterStruct> UBC; //UBC : 9 registers
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extern Array<RegisterStruct> BSC; //BSC : 18 registers
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extern Array<RegisterStruct> DMAC; //DMAC : 17 registers
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extern Array<RegisterStruct> CPG; //CPG : 5 registers
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extern Array<RegisterStruct> RTC; //RTC : 16 registers
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extern Array<RegisterStruct> INTC; //INTC : 4 registers
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extern Array<RegisterStruct> TMU; //TMU : 12 registers
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extern Array<RegisterStruct> SCI; //SCI : 8 registers
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extern Array<RegisterStruct> SCIF; //SCIF : 10 registers
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extern std::array<RegisterStruct, 18> CCN;
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extern std::array<RegisterStruct, 9> UBC;
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extern std::array<RegisterStruct, 19> BSC;
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extern std::array<RegisterStruct, 17> DMAC;
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extern std::array<RegisterStruct, 5> CPG;
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extern std::array<RegisterStruct, 16> RTC;
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extern std::array<RegisterStruct, 5> INTC;
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extern std::array<RegisterStruct, 12> TMU;
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extern std::array<RegisterStruct, 8> SCI;
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extern std::array<RegisterStruct, 10> SCIF;
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/*
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//Region P4
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@ -38,7 +39,8 @@ void sh4_mmr_init();
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void sh4_mmr_reset(bool hard);
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void sh4_mmr_term();
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void sh4_rio_reg(Array<RegisterStruct>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rp=0, RegWriteAddrFP* wp=0);
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template<typename T>
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void sh4_rio_reg(T& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rp=0, RegWriteAddrFP* wp=0);
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#define A7_REG_HASH(addr) ((addr>>16)&0x1FFF)
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@ -5,6 +5,7 @@
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#include "hw/aica/aica.h"
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#include "hw/aica/sgc_if.h"
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#include "hw/arm7/arm7.h"
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#include "hw/holly/sb.h"
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#include "hw/holly/sb_mem.h"
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#include "hw/flashrom/flashrom.h"
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#include "hw/mem/_vmem.h"
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@ -69,7 +70,6 @@ extern s16 cdda_sector[CDDA_SIZE];
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extern u32 cdda_index;
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//./core/hw/holly/sb.o
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extern Array<RegisterStruct> sb_regs;
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extern u32 SB_ISTNRM;
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extern u32 SB_FFST_rc;
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extern u32 SB_FFST;
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@ -151,17 +151,7 @@ extern bool pal_needs_update;
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extern VArray2 vram;
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//./core/hw/sh4/sh4_mmr.o
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extern Array<u8> OnChipRAM;
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extern Array<RegisterStruct> CCN; //CCN : 14 registers
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extern Array<RegisterStruct> UBC; //UBC : 9 registers
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extern Array<RegisterStruct> BSC; //BSC : 18 registers
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extern Array<RegisterStruct> DMAC; //DMAC : 17 registers
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extern Array<RegisterStruct> CPG; //CPG : 5 registers
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extern Array<RegisterStruct> RTC; //RTC : 16 registers
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extern Array<RegisterStruct> INTC; //INTC : 4 registers
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extern Array<RegisterStruct> TMU; //TMU : 12 registers
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extern Array<RegisterStruct> SCI; //SCI : 8 registers
|
||||
extern Array<RegisterStruct> SCIF; //SCIF : 10 registers
|
||||
extern std::array<u8, OnChipRAM_SIZE> OnChipRAM;
|
||||
|
||||
//./core/hw/sh4/sh4_mem.o
|
||||
extern VArray2 mem_b;
|
||||
|
|
@ -241,7 +231,7 @@ extern u32 reg_dimm_parameterl;
|
|||
extern u32 reg_dimm_parameterh;
|
||||
extern u32 reg_dimm_status;
|
||||
|
||||
bool rc_serialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size)
|
||||
bool rc_serialize(const void *src, unsigned int src_size, void **dest, unsigned int *total_size)
|
||||
{
|
||||
if ( *dest != NULL )
|
||||
{
|
||||
|
|
@ -265,33 +255,30 @@ bool rc_unserialize(void *src, unsigned int src_size, void **dest, unsigned int
|
|||
return true ;
|
||||
}
|
||||
|
||||
bool register_serialize(Array<RegisterStruct>& regs,void **data, unsigned int *total_size )
|
||||
template<typename T>
|
||||
bool register_serialize(const T& regs,void **data, unsigned int *total_size )
|
||||
{
|
||||
int i = 0 ;
|
||||
for (const auto& reg : regs)
|
||||
REICAST_S(reg.data32);
|
||||
|
||||
for ( i = 0 ; i < regs.Size ; i++ )
|
||||
{
|
||||
REICAST_S(regs.data[i].data32) ;
|
||||
}
|
||||
|
||||
return true ;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool register_unserialize(Array<RegisterStruct>& regs,void **data, unsigned int *total_size, serialize_version_enum version)
|
||||
template<typename T>
|
||||
bool register_unserialize(T& regs,void **data, unsigned int *total_size, serialize_version_enum version)
|
||||
{
|
||||
int i = 0 ;
|
||||
u32 dummy = 0 ;
|
||||
u32 dummy = 0;
|
||||
|
||||
for ( i = 0 ; i < regs.Size ; i++ )
|
||||
for (auto& reg : regs)
|
||||
{
|
||||
if (version < V5)
|
||||
REICAST_US(dummy); // regs.data[i].flags
|
||||
if ( ! (regs.data[i].flags & REG_RF) )
|
||||
REICAST_US(regs.data[i].data32) ;
|
||||
if (!(reg.flags & REG_RF))
|
||||
REICAST_US(reg.data32);
|
||||
else
|
||||
REICAST_US(dummy) ;
|
||||
REICAST_US(dummy);
|
||||
}
|
||||
return true ;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool dc_serialize(void **data, unsigned int *total_size)
|
||||
|
|
@ -403,7 +390,7 @@ bool dc_serialize(void **data, unsigned int *total_size)
|
|||
|
||||
REICAST_SA(vram.data, vram.size);
|
||||
|
||||
REICAST_SA(OnChipRAM.data,OnChipRAM_SIZE);
|
||||
REICAST_SA(OnChipRAM.data(), OnChipRAM_SIZE);
|
||||
|
||||
register_serialize(CCN, data, total_size) ;
|
||||
register_serialize(UBC, data, total_size) ;
|
||||
|
|
@ -664,7 +651,7 @@ static bool dc_unserialize_libretro(void **data, unsigned int *total_size)
|
|||
|
||||
REICAST_USA(vram.data, vram.size);
|
||||
|
||||
REICAST_USA(OnChipRAM.data,OnChipRAM_SIZE);
|
||||
REICAST_USA(OnChipRAM.data(), OnChipRAM_SIZE);
|
||||
|
||||
register_unserialize(CCN, data, total_size, V9_LIBRETRO) ;
|
||||
register_unserialize(UBC, data, total_size, V9_LIBRETRO) ;
|
||||
|
|
@ -987,7 +974,7 @@ bool dc_unserialize(void **data, unsigned int *total_size)
|
|||
REICAST_USA(vram.data, vram.size);
|
||||
pal_needs_update = true;
|
||||
|
||||
REICAST_USA(OnChipRAM.data,OnChipRAM_SIZE);
|
||||
REICAST_USA(OnChipRAM.data(), OnChipRAM_SIZE);
|
||||
|
||||
register_unserialize(CCN, data, total_size, version) ;
|
||||
register_unserialize(UBC, data, total_size, version) ;
|
||||
|
|
|
|||
141
core/stdclass.h
141
core/stdclass.h
|
|
@ -20,147 +20,6 @@
|
|||
#define PAGE_MASK (PAGE_SIZE-1)
|
||||
#endif
|
||||
|
||||
//Commonly used classes across the project
|
||||
//Simple Array class for helping me out ;P
|
||||
template<class T>
|
||||
class Array
|
||||
{
|
||||
public:
|
||||
T* data;
|
||||
u32 Size;
|
||||
|
||||
Array(T* Source,u32 ellements)
|
||||
{
|
||||
//initialise array
|
||||
data=Source;
|
||||
Size=ellements;
|
||||
}
|
||||
|
||||
Array(u32 ellements)
|
||||
{
|
||||
//initialise array
|
||||
data=0;
|
||||
Resize(ellements,false);
|
||||
Size=ellements;
|
||||
}
|
||||
|
||||
Array(u32 ellements,bool zero)
|
||||
{
|
||||
//initialise array
|
||||
data=0;
|
||||
Resize(ellements,zero);
|
||||
Size=ellements;
|
||||
}
|
||||
|
||||
Array()
|
||||
{
|
||||
//initialise array
|
||||
data=0;
|
||||
Size=0;
|
||||
}
|
||||
|
||||
~Array()
|
||||
{
|
||||
if (data)
|
||||
{
|
||||
#ifdef MEM_ALLOC_TRACE
|
||||
DEBUG_LOG(COMMON, "WARNING : DESTRUCTOR WITH NON FREED ARRAY [arrayid:%d]", id);
|
||||
#endif
|
||||
Free();
|
||||
}
|
||||
}
|
||||
|
||||
void SetPtr(T* Source,u32 ellements)
|
||||
{
|
||||
//initialise array
|
||||
Free();
|
||||
data=Source;
|
||||
Size=ellements;
|
||||
}
|
||||
|
||||
T* Resize(u32 size,bool bZero)
|
||||
{
|
||||
if (size==0)
|
||||
{
|
||||
if (data)
|
||||
{
|
||||
#ifdef MEM_ALLOC_TRACE
|
||||
DEBUG_LOG(COMMON, "Freeing data -> resize to zero[Array:%d]", id);
|
||||
#endif
|
||||
Free();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (!data)
|
||||
data=(T*)malloc(size*sizeof(T));
|
||||
else
|
||||
data=(T*)realloc(data,size*sizeof(T));
|
||||
|
||||
//TODO : Optimise this
|
||||
//if we allocated more , Zero it out
|
||||
if (bZero)
|
||||
{
|
||||
if (size>Size)
|
||||
{
|
||||
for (u32 i=Size;i<size;i++)
|
||||
{
|
||||
u8*p =(u8*)&data[i];
|
||||
for (size_t j=0;j<sizeof(T);j++)
|
||||
{
|
||||
p[j]=0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Size=size;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void Zero()
|
||||
{
|
||||
memset(data,0,sizeof(T)*Size);
|
||||
}
|
||||
|
||||
void Free()
|
||||
{
|
||||
if (Size != 0)
|
||||
{
|
||||
if (data)
|
||||
free(data);
|
||||
|
||||
data = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
INLINE T& operator [](const u32 i)
|
||||
{
|
||||
#ifdef MEM_BOUND_CHECK
|
||||
if (i>=Size)
|
||||
{
|
||||
ERROR_LOG(COMMON, "Error: Array %d , index out of range (%d > %d)", id, i, Size - 1);
|
||||
MEM_DO_BREAK;
|
||||
}
|
||||
#endif
|
||||
return data[i];
|
||||
}
|
||||
|
||||
INLINE T& operator [](const s32 i)
|
||||
{
|
||||
#ifdef MEM_BOUND_CHECK
|
||||
if (!(i>=0 && i<(s32)Size))
|
||||
{
|
||||
ERROR_LOG(COMMON, "Error: Array %d , index out of range (%d > %d)", id, i, Size - 1);
|
||||
MEM_DO_BREAK;
|
||||
}
|
||||
#endif
|
||||
return data[i];
|
||||
}
|
||||
};
|
||||
|
||||
//Windoze code
|
||||
//Threads
|
||||
|
||||
#if !defined(HOST_NO_THREADS)
|
||||
|
|
|
|||
|
|
@ -302,7 +302,7 @@ using namespace std;
|
|||
void os_DebugBreak();
|
||||
#define dbgbreak os_DebugBreak()
|
||||
|
||||
bool rc_serialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size) ;
|
||||
bool rc_serialize(const void *src, unsigned int src_size, void **dest, unsigned int *total_size) ;
|
||||
bool rc_unserialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size);
|
||||
bool dc_serialize(void **data, unsigned int *total_size);
|
||||
bool dc_unserialize(void **data, unsigned int *total_size);
|
||||
|
|
@ -341,8 +341,6 @@ typedef void RegWriteAddrFP(u32 addr, u32 data);
|
|||
*/
|
||||
enum RegStructFlags
|
||||
{
|
||||
REG_ACCESS_32=4,
|
||||
|
||||
REG_RF=8,
|
||||
REG_WF=16,
|
||||
REG_RO=32,
|
||||
|
|
|
|||
Loading…
Reference in New Issue