From 0d9214df408f64c4062d03d2fd1f528e522b927a Mon Sep 17 00:00:00 2001 From: Flyinghead Date: Sat, 25 Jan 2020 11:00:34 +0100 Subject: [PATCH] replace Array with std::array --- core/hw/holly/sb.cpp | 18 ++--- core/hw/holly/sb.h | 5 +- core/hw/sh4/sh4_mmr.cpp | 140 +++++++++++++++++++++++---------------- core/hw/sh4/sh4_mmr.h | 24 +++---- core/serialize.cpp | 51 ++++++--------- core/stdclass.h | 141 ---------------------------------------- core/types.h | 4 +- 7 files changed, 128 insertions(+), 255 deletions(-) diff --git a/core/hw/holly/sb.cpp b/core/hw/holly/sb.cpp index 2a0ea9a58..3924be918 100644 --- a/core/hw/holly/sb.cpp +++ b/core/hw/holly/sb.cpp @@ -16,7 +16,7 @@ extern void dc_request_reset(); -Array sb_regs(0x540); +std::array sb_regs; //(addr>= 0x005F6800) && (addr<=0x005F7CFF) -> 0x1500 bytes -> 0x540 possible registers , 125 actually exist only // System Control Reg. //0x100 bytes @@ -127,9 +127,9 @@ void sb_rio_register(u32 reg_addr, RegIO flags, RegReadAddrFP* rf, RegWriteAddrF { u32 idx=(reg_addr-SB_BASE)/4; - verify(idx #include "types.h" @@ -13,7 +14,7 @@ void sb_Init(); void sb_Reset(bool hard); void sb_Term(); -extern Array sb_regs; +extern std::array sb_regs; #define SB_BASE 0x005F6800 @@ -314,7 +315,7 @@ extern Array sb_regs; //0x005F7CF8 SB_PDLEND R PVR-DMA transfer counter #define SB_PDLEND_addr 0x005F7CF8 -#define SB_REGN_32(addr) (sb_regs[(addr-SB_BASE)/4].data32) +#define SB_REGN_32(addr) (sb_regs[((addr) - SB_BASE) / 4].data32) #define SB_REG_32(name) SB_REGN_32(SB_##name##_addr) #define SB_REG_T(name) ((SB_name##_t&)SB_REG_T(name)) diff --git a/core/hw/sh4/sh4_mmr.cpp b/core/hw/sh4/sh4_mmr.cpp index b3db050ca..ab0d403b8 100644 --- a/core/hw/sh4/sh4_mmr.cpp +++ b/core/hw/sh4/sh4_mmr.cpp @@ -1,6 +1,7 @@ /* Sh4 internal register routing (P4 & 'area 7') */ +#include #include "types.h" #include "sh4_mmr.h" @@ -11,45 +12,44 @@ //64bytes of sq // now on context ~ -Array OnChipRAM; +std::array OnChipRAM; //All registers are 4 byte aligned -Array CCN(18,true); //CCN : 16 registers -Array UBC(9,true); //UBC : 9 registers -Array BSC(19,true); //BSC : 18 registers -Array DMAC(17,true); //DMAC : 17 registers -Array CPG(5,true); //CPG : 5 registers -Array RTC(16,true); //RTC : 16 registers -Array INTC(5,true); //INTC : 5 registers -Array TMU(12,true); //TMU : 12 registers -Array SCI(8,true); //SCI : 8 registers -Array SCIF(10,true); //SCIF : 10 registers +std::array CCN; +std::array UBC; +std::array BSC; +std::array DMAC; +std::array CPG; +std::array RTC; +std::array INTC; +std::array TMU; +std::array SCI; +std::array SCIF; -Array * const AllRegisters[] = { &CCN, &UBC, &BSC, &DMAC, &CPG, &RTC, &INTC, &TMU, &SCI, &SCIF }; - -u32 sh4io_read_noacc(u32 addr) +static u32 sh4io_read_noacc(u32 addr) { INFO_LOG(SH4, "sh4io: Invalid read access @@ %08X", addr); return 0; } -void sh4io_write_noacc(u32 addr, u32 data) +static void sh4io_write_noacc(u32 addr, u32 data) { INFO_LOG(SH4, "sh4io: Invalid write access @@ %08X %08X", addr, data); //verify(false); } -void sh4io_write_const(u32 addr, u32 data) +static void sh4io_write_const(u32 addr, u32 data) { INFO_LOG(SH4, "sh4io: Const write ignored @@ %08X <- %08X", addr, data); } -void sh4_rio_reg(Array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf) +template +void sh4_rio_reg(T& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf) { u32 idx=(addr&255)/4; - verify(idx& arr, u32 addr, RegIO flags, u32 sz, RegR arr[idx].writeFunctionAddr=wf==0?&sh4io_write_noacc:wf; } } +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); +template void sh4_rio_reg(std::array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf); -template -u32 sh4_rio_read(Array& sb_regs, u32 addr) +template +u32 sh4_rio_read(T& regs, u32 addr) { u32 offset = addr&255; #ifdef TRACE @@ -86,21 +95,21 @@ u32 sh4_rio_read(Array& sb_regs, u32 addr) offset>>=2; #ifdef TRACE - if (sb_regs[offset].flags & sz) + if (regs[offset].flags & sz) { #endif - if (!(sb_regs[offset].flags & REG_RF) ) + if (!(regs[offset].flags & REG_RF) ) { if (sz==4) - return sb_regs[offset].data32; + return regs[offset].data32; else if (sz==2) - return sb_regs[offset].data16; + return regs[offset].data16; else - return sb_regs[offset].data8; + return regs[offset].data8; } else { - return sb_regs[offset].readFunctionAddr(addr); + return regs[offset].readFunctionAddr(addr); } #ifdef TRACE } @@ -112,8 +121,8 @@ u32 sh4_rio_read(Array& sb_regs, u32 addr) return 0; } -template -void sh4_rio_write(Array& sb_regs, u32 addr, u32 data) +template +void sh4_rio_write(T& regs, u32 addr, u32 data) { u32 offset = addr&255; #ifdef TRACE @@ -124,23 +133,23 @@ void sh4_rio_write(Array& sb_regs, u32 addr, u32 data) #endif offset>>=2; #ifdef TRACE - if (sb_regs[offset].flags & sz) + if (regs[offset].flags & sz) { #endif - if (!(sb_regs[offset].flags & REG_WF) ) + if (!(regs[offset].flags & REG_WF) ) { if (sz==4) - sb_regs[offset].data32=data; + regs[offset].data32=data; else if (sz==2) - sb_regs[offset].data16=(u16)data; + regs[offset].data16=(u16)data; else - sb_regs[offset].data8=(u8)data; + regs[offset].data8=(u8)data; return; } else { //printf("RSW: %08X\n",addr); - sb_regs[offset].writeFunctionAddr(addr,data); + regs[offset].writeFunctionAddr(addr,data); return; } #ifdef TRACE @@ -794,25 +803,30 @@ void DYNACALL WriteMem_area7_OCR_T(u32 addr,T data) } } +template +static void init_regs(T& regs) +{ + for (auto& reg : regs) + { + reg.flags = RIO_NO_ACCESS; + reg.readFunctionAddr = &sh4io_read_noacc; + reg.writeFunctionAddr = &sh4io_write_noacc; + } +} //Init/Res/Term void sh4_mmr_init() { - OnChipRAM.Resize(OnChipRAM_SIZE,false); - - for (u32 i=0;i<30;i++) - { - if (iSize; j++) - (*AllRegisters[i])[j].reset(); + for (auto& reg : CCN) + reg.reset(); + for (auto& reg : UBC) + reg.reset(); + for (auto& reg : BSC) + reg.reset(); + for (auto& reg : DMAC) + reg.reset(); + for (auto& reg : CPG) + reg.reset(); + for (auto& reg : RTC) + reg.reset(); + for (auto& reg : INTC) + reg.reset(); + for (auto& reg : TMU) + reg.reset(); + for (auto& reg : SCI) + reg.reset(); + for (auto& reg : SCIF) + reg.reset(); } - OnChipRAM.Zero(); + OnChipRAM = {}; //Reset register values bsc_reset(hard); ccn_reset(); @@ -859,7 +890,6 @@ void sh4_mmr_term() cpg_term(); ccn_term(); bsc_term(); - OnChipRAM.Free(); } //Mem map :) diff --git a/core/hw/sh4/sh4_mmr.h b/core/hw/sh4/sh4_mmr.h index f308f8141..29458a2a4 100644 --- a/core/hw/sh4/sh4_mmr.h +++ b/core/hw/sh4/sh4_mmr.h @@ -1,4 +1,5 @@ #pragma once +#include #include "types.h" #include "../sh4/sh4_if.h" @@ -12,16 +13,16 @@ void map_p4(); #define sq_both ((u8*)sh4rcb.sq_buffer) -extern Array CCN; //CCN : 14 registers -extern Array UBC; //UBC : 9 registers -extern Array BSC; //BSC : 18 registers -extern Array DMAC; //DMAC : 17 registers -extern Array CPG; //CPG : 5 registers -extern Array RTC; //RTC : 16 registers -extern Array INTC; //INTC : 4 registers -extern Array TMU; //TMU : 12 registers -extern Array SCI; //SCI : 8 registers -extern Array SCIF; //SCIF : 10 registers +extern std::array CCN; +extern std::array UBC; +extern std::array BSC; +extern std::array DMAC; +extern std::array CPG; +extern std::array RTC; +extern std::array INTC; +extern std::array TMU; +extern std::array SCI; +extern std::array SCIF; /* //Region P4 @@ -38,7 +39,8 @@ void sh4_mmr_init(); void sh4_mmr_reset(bool hard); void sh4_mmr_term(); -void sh4_rio_reg(Array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rp=0, RegWriteAddrFP* wp=0); +template +void sh4_rio_reg(T& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rp=0, RegWriteAddrFP* wp=0); #define A7_REG_HASH(addr) ((addr>>16)&0x1FFF) diff --git a/core/serialize.cpp b/core/serialize.cpp index 75f6bfd41..6bedf1d5c 100644 --- a/core/serialize.cpp +++ b/core/serialize.cpp @@ -5,6 +5,7 @@ #include "hw/aica/aica.h" #include "hw/aica/sgc_if.h" #include "hw/arm7/arm7.h" +#include "hw/holly/sb.h" #include "hw/holly/sb_mem.h" #include "hw/flashrom/flashrom.h" #include "hw/mem/_vmem.h" @@ -69,7 +70,6 @@ extern s16 cdda_sector[CDDA_SIZE]; extern u32 cdda_index; //./core/hw/holly/sb.o -extern Array sb_regs; extern u32 SB_ISTNRM; extern u32 SB_FFST_rc; extern u32 SB_FFST; @@ -151,17 +151,7 @@ extern bool pal_needs_update; extern VArray2 vram; //./core/hw/sh4/sh4_mmr.o -extern Array OnChipRAM; -extern Array CCN; //CCN : 14 registers -extern Array UBC; //UBC : 9 registers -extern Array BSC; //BSC : 18 registers -extern Array DMAC; //DMAC : 17 registers -extern Array CPG; //CPG : 5 registers -extern Array RTC; //RTC : 16 registers -extern Array INTC; //INTC : 4 registers -extern Array TMU; //TMU : 12 registers -extern Array SCI; //SCI : 8 registers -extern Array SCIF; //SCIF : 10 registers +extern std::array OnChipRAM; //./core/hw/sh4/sh4_mem.o extern VArray2 mem_b; @@ -241,7 +231,7 @@ extern u32 reg_dimm_parameterl; extern u32 reg_dimm_parameterh; extern u32 reg_dimm_status; -bool rc_serialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size) +bool rc_serialize(const void *src, unsigned int src_size, void **dest, unsigned int *total_size) { if ( *dest != NULL ) { @@ -265,33 +255,30 @@ bool rc_unserialize(void *src, unsigned int src_size, void **dest, unsigned int return true ; } -bool register_serialize(Array& regs,void **data, unsigned int *total_size ) +template +bool register_serialize(const T& regs,void **data, unsigned int *total_size ) { - int i = 0 ; + for (const auto& reg : regs) + REICAST_S(reg.data32); - for ( i = 0 ; i < regs.Size ; i++ ) - { - REICAST_S(regs.data[i].data32) ; - } - - return true ; + return true; } -bool register_unserialize(Array& regs,void **data, unsigned int *total_size, serialize_version_enum version) +template +bool register_unserialize(T& regs,void **data, unsigned int *total_size, serialize_version_enum version) { - int i = 0 ; - u32 dummy = 0 ; + u32 dummy = 0; - for ( i = 0 ; i < regs.Size ; i++ ) + for (auto& reg : regs) { if (version < V5) REICAST_US(dummy); // regs.data[i].flags - if ( ! (regs.data[i].flags & REG_RF) ) - REICAST_US(regs.data[i].data32) ; + if (!(reg.flags & REG_RF)) + REICAST_US(reg.data32); else - REICAST_US(dummy) ; + REICAST_US(dummy); } - return true ; + return true; } bool dc_serialize(void **data, unsigned int *total_size) @@ -403,7 +390,7 @@ bool dc_serialize(void **data, unsigned int *total_size) REICAST_SA(vram.data, vram.size); - REICAST_SA(OnChipRAM.data,OnChipRAM_SIZE); + REICAST_SA(OnChipRAM.data(), OnChipRAM_SIZE); register_serialize(CCN, data, total_size) ; register_serialize(UBC, data, total_size) ; @@ -664,7 +651,7 @@ static bool dc_unserialize_libretro(void **data, unsigned int *total_size) REICAST_USA(vram.data, vram.size); - REICAST_USA(OnChipRAM.data,OnChipRAM_SIZE); + REICAST_USA(OnChipRAM.data(), OnChipRAM_SIZE); register_unserialize(CCN, data, total_size, V9_LIBRETRO) ; register_unserialize(UBC, data, total_size, V9_LIBRETRO) ; @@ -987,7 +974,7 @@ bool dc_unserialize(void **data, unsigned int *total_size) REICAST_USA(vram.data, vram.size); pal_needs_update = true; - REICAST_USA(OnChipRAM.data,OnChipRAM_SIZE); + REICAST_USA(OnChipRAM.data(), OnChipRAM_SIZE); register_unserialize(CCN, data, total_size, version) ; register_unserialize(UBC, data, total_size, version) ; diff --git a/core/stdclass.h b/core/stdclass.h index 0ab70168b..fdce63b08 100644 --- a/core/stdclass.h +++ b/core/stdclass.h @@ -20,147 +20,6 @@ #define PAGE_MASK (PAGE_SIZE-1) #endif -//Commonly used classes across the project -//Simple Array class for helping me out ;P -template -class Array -{ -public: - T* data; - u32 Size; - - Array(T* Source,u32 ellements) - { - //initialise array - data=Source; - Size=ellements; - } - - Array(u32 ellements) - { - //initialise array - data=0; - Resize(ellements,false); - Size=ellements; - } - - Array(u32 ellements,bool zero) - { - //initialise array - data=0; - Resize(ellements,zero); - Size=ellements; - } - - Array() - { - //initialise array - data=0; - Size=0; - } - - ~Array() - { - if (data) - { - #ifdef MEM_ALLOC_TRACE - DEBUG_LOG(COMMON, "WARNING : DESTRUCTOR WITH NON FREED ARRAY [arrayid:%d]", id); - #endif - Free(); - } - } - - void SetPtr(T* Source,u32 ellements) - { - //initialise array - Free(); - data=Source; - Size=ellements; - } - - T* Resize(u32 size,bool bZero) - { - if (size==0) - { - if (data) - { - #ifdef MEM_ALLOC_TRACE - DEBUG_LOG(COMMON, "Freeing data -> resize to zero[Array:%d]", id); - #endif - Free(); - } - - } - - if (!data) - data=(T*)malloc(size*sizeof(T)); - else - data=(T*)realloc(data,size*sizeof(T)); - - //TODO : Optimise this - //if we allocated more , Zero it out - if (bZero) - { - if (size>Size) - { - for (u32 i=Size;i=Size) - { - ERROR_LOG(COMMON, "Error: Array %d , index out of range (%d > %d)", id, i, Size - 1); - MEM_DO_BREAK; - } -#endif - return data[i]; - } - - INLINE T& operator [](const s32 i) - { -#ifdef MEM_BOUND_CHECK - if (!(i>=0 && i<(s32)Size)) - { - ERROR_LOG(COMMON, "Error: Array %d , index out of range (%d > %d)", id, i, Size - 1); - MEM_DO_BREAK; - } -#endif - return data[i]; - } -}; - -//Windoze code //Threads #if !defined(HOST_NO_THREADS) diff --git a/core/types.h b/core/types.h index 8fc7ef0e5..18da2ae32 100644 --- a/core/types.h +++ b/core/types.h @@ -302,7 +302,7 @@ using namespace std; void os_DebugBreak(); #define dbgbreak os_DebugBreak() -bool rc_serialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size) ; +bool rc_serialize(const void *src, unsigned int src_size, void **dest, unsigned int *total_size) ; bool rc_unserialize(void *src, unsigned int src_size, void **dest, unsigned int *total_size); bool dc_serialize(void **data, unsigned int *total_size); bool dc_unserialize(void **data, unsigned int *total_size); @@ -341,8 +341,6 @@ typedef void RegWriteAddrFP(u32 addr, u32 data); */ enum RegStructFlags { - REG_ACCESS_32=4, - REG_RF=8, REG_WF=16, REG_RO=32,