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aica arm dynarec: conditional LDR with write back issue

This commit is contained in:
Flyinghead 2021-05-16 20:21:09 +02:00
parent da40297810
commit 00a74d81c2
2 changed files with 12 additions and 1 deletions
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3
core/hw/arm7/arm7_rec.cpp
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@ -518,7 +518,8 @@ static void block_ssa_pass()
newop.arg[1] = it->arg[1];
if (it->arg[1].shift_type == ArmOp::RRX && it->arg[1].shift_value == 0)
newop.flags |= ArmOp::OP_READS_FLAGS;
it->flags &= ~ArmOp::OP_READS_FLAGS;
if (it->condition == ArmOp::AL)
it->flags &= ~ArmOp::OP_READS_FLAGS;
it->write_back = false;
it->arg[1] = ArmOp::Operand();
if (it->pre_index)

10
tests/src/AicaArmTest.cpp
View File

@ -743,6 +743,16 @@ TEST_F(AicaArmTest, MemoryTest)
RunOp();
ASSERT_EQ(arm_Reg[0].I, (*(u32*)&aica_ram[0x1004]) >> 16 | (*(u32*)&aica_ram[0x1004]) << 16);
ASSERT_EQ(arm_Reg[2].I, 1);
// conditional with write-back, false condition
PrepareOp(0x04910004); // ldreq r0, [r1], #4
ResetNZCV();
arm_Reg[0].I = 0;
arm_Reg[1].I = 0x1004;
RunOp();
ASSERT_EQ(arm_Reg[0].I, 0);
ASSERT_EQ(arm_Reg[1].I, 0x1004);
}
TEST_F(AicaArmTest, PcRelativeTest)