diff --git a/core/hw/arm7/arm7_rec.cpp b/core/hw/arm7/arm7_rec.cpp
index 122043b23..a14b42110 100644
--- a/core/hw/arm7/arm7_rec.cpp
+++ b/core/hw/arm7/arm7_rec.cpp
@@ -518,7 +518,8 @@ static void block_ssa_pass()
 					newop.arg[1] = it->arg[1];
 					if (it->arg[1].shift_type == ArmOp::RRX && it->arg[1].shift_value == 0)
 						newop.flags |= ArmOp::OP_READS_FLAGS;
-					it->flags &= ~ArmOp::OP_READS_FLAGS;
+					if (it->condition == ArmOp::AL)
+						it->flags &= ~ArmOp::OP_READS_FLAGS;
 					it->write_back = false;
 					it->arg[1] = ArmOp::Operand();
 					if (it->pre_index)
diff --git a/tests/src/AicaArmTest.cpp b/tests/src/AicaArmTest.cpp
index a786ae60a..d146ac414 100644
--- a/tests/src/AicaArmTest.cpp
+++ b/tests/src/AicaArmTest.cpp
@@ -743,6 +743,16 @@ TEST_F(AicaArmTest, MemoryTest)
 	RunOp();
 	ASSERT_EQ(arm_Reg[0].I, (*(u32*)&aica_ram[0x1004]) >> 16 | (*(u32*)&aica_ram[0x1004]) << 16);
 	ASSERT_EQ(arm_Reg[2].I, 1);
+
+	// conditional with write-back, false condition
+	PrepareOp(0x04910004);	// ldreq r0, [r1], #4
+	ResetNZCV();
+	arm_Reg[0].I = 0;
+	arm_Reg[1].I = 0x1004;
+	RunOp();
+	ASSERT_EQ(arm_Reg[0].I, 0);
+	ASSERT_EQ(arm_Reg[1].I, 0x1004);
+
 }
 
 TEST_F(AicaArmTest, PcRelativeTest)