CPU: Declare state with constinit
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@ -98,7 +98,7 @@ static bool WriteMemoryByte(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryHalfWord(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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static bool WriteMemoryWord(VirtualMemoryAddress addr, u32 value);
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alignas(HOST_CACHE_LINE_SIZE) State g_state;
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constinit State g_state;
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bool TRACE_EXECUTION = false;
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bool TRACE_EXECUTION = false;
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static fastjmp_buf s_jmp_buf;
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static fastjmp_buf s_jmp_buf;
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@ -70,7 +70,7 @@ struct PGXPValue
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}
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}
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};
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};
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struct State
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struct ALIGN_TO_CACHE_LINE State
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{
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{
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// ticks the CPU has executed
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// ticks the CPU has executed
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u32 downcount = 0;
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u32 downcount = 0;
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@ -80,8 +80,8 @@ struct State
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Registers regs = {};
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Registers regs = {};
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Cop0Registers cop0_regs = {};
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Cop0Registers cop0_regs = {};
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u32 pc; // at execution time: the address of the next instruction to execute (already fetched)
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u32 pc = 0; // at execution time: the address of the next instruction to execute (already fetched)
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u32 npc; // at execution time: the address of the next instruction to fetch
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u32 npc = 0; // at execution time: the address of the next instruction to fetch
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// address of the instruction currently being executed
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// address of the instruction currently being executed
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Instruction current_instruction = {};
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Instruction current_instruction = {};
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@ -125,7 +125,7 @@ struct State
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static constexpr u32 GTERegisterOffset(u32 index) { return OFFSETOF(State, gte_regs.r32) + (sizeof(u32) * index); }
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static constexpr u32 GTERegisterOffset(u32 index) { return OFFSETOF(State, gte_regs.r32) + (sizeof(u32) * index); }
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};
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};
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ALIGN_TO_CACHE_LINE extern State g_state;
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extern State g_state;
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void Initialize();
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void Initialize();
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void Shutdown();
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void Shutdown();
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