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CPU/Recompiler: Don't use far code for mtc0 cache check 

Redundant for a few instructions.
This commit is contained in:
Stenzek 2024-12-19 18:21:59 +10:00
parent fe1fa765f7
commit 10e2079ee4
No known key found for this signature in database
4 changed files with 22 additions and 11 deletions
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8
src/core/cpu_recompiler_arm32.cpp
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@ -2265,15 +2265,19 @@ void CPU::ARM32Recompiler::Compile_mtc0(CompileFlags cf)
// We could just inline the whole thing.. // We could just inline the whole thing..
Flush(FLUSH_FOR_C_CALL); Flush(FLUSH_FOR_C_CALL);
SwitchToFarCodeIfBitSet(changed_bits, 16); Label caches_unchanged;
armAsm->tst(changed_bits, 1u << 16);
armAsm->b(eq, &caches_unchanged);
EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers)); EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
armAsm->ldr(RARG1, PTR(ptr)); // reload value for interrupt test below armAsm->ldr(RARG1, PTR(ptr)); // reload value for interrupt test below
armAsm->bind(&caches_unchanged);
// might need to reload fastmem base too
if (CodeCache::IsUsingFastmem() && m_block->HasFlag(CodeCache::BlockFlags::ContainsLoadStoreInstructions) && if (CodeCache::IsUsingFastmem() && m_block->HasFlag(CodeCache::BlockFlags::ContainsLoadStoreInstructions) &&
IsHostRegAllocated(RMEMBASE.GetCode())) IsHostRegAllocated(RMEMBASE.GetCode()))
{ {
FreeHostReg(RMEMBASE.GetCode()); FreeHostReg(RMEMBASE.GetCode());
} }
SwitchToNearCode(true);
TestInterrupts(RARG1); TestInterrupts(RARG1);
} }

6
src/core/cpu_recompiler_arm64.cpp
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@ -2428,11 +2428,13 @@ void CPU::ARM64Recompiler::Compile_mtc0(CompileFlags cf)
// We could just inline the whole thing.. // We could just inline the whole thing..
Flush(FLUSH_FOR_C_CALL); Flush(FLUSH_FOR_C_CALL);
SwitchToFarCodeIfBitSet(changed_bits, 16); Label caches_unchanged;
armAsm->tbz(changed_bits, 16, &caches_unchanged);
EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers)); EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
armAsm->ldr(RWARG1, PTR(ptr)); // reload value for interrupt test below armAsm->ldr(RWARG1, PTR(ptr)); // reload value for interrupt test below
if (CodeCache::IsUsingFastmem())
armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base)); armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base));
SwitchToNearCode(true); armAsm->bind(&caches_unchanged);
TestInterrupts(RWARG1); TestInterrupts(RWARG1);
} }

6
src/core/cpu_recompiler_riscv64.cpp
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@ -2283,13 +2283,15 @@ void CPU::RISCV64Recompiler::Compile_mtc0(CompileFlags cf)
// We could just inline the whole thing.. // We could just inline the whole thing..
Flush(FLUSH_FOR_C_CALL); Flush(FLUSH_FOR_C_CALL);
Label caches_unchanged;
rvAsm->SRLIW(RSCRATCH, changed_bits, 16); rvAsm->SRLIW(RSCRATCH, changed_bits, 16);
rvAsm->ANDI(RSCRATCH, RSCRATCH, 1); rvAsm->ANDI(RSCRATCH, RSCRATCH, 1);
SwitchToFarCode(true, &Assembler::BEQ, RSCRATCH, zero); rvAsm->BEQ(RSCRATCH, zero, &caches_unchanged);
EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers)); EmitCall(reinterpret_cast<const void*>(&CPU::UpdateMemoryPointers));
rvAsm->LW(new_value, PTR(ptr)); rvAsm->LW(new_value, PTR(ptr));
if (CodeCache::IsUsingFastmem())
rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base)); rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base));
SwitchToNearCode(true); rvAsm->Bind(&caches_unchanged);
TestInterrupts(RARG1); TestInterrupts(RARG1);
} }

7
src/core/cpu_recompiler_x64.cpp
View File

@ -2241,12 +2241,15 @@ void CPU::X64Recompiler::Compile_mtc0(CompileFlags cf)
// We could just inline the whole thing.. // We could just inline the whole thing..
Flush(FLUSH_FOR_C_CALL); Flush(FLUSH_FOR_C_CALL);
Label caches_unchanged;
cg->test(changed_bits, 1u << 16); cg->test(changed_bits, 1u << 16);
SwitchToFarCode(true, &CodeGenerator::jnz); cg->jz(caches_unchanged);
cg->call(&CPU::UpdateMemoryPointers); cg->call(&CPU::UpdateMemoryPointers);
cg->mov(RWARG2, cg->dword[PTR(ptr)]); // reload value for interrupt test below cg->mov(RWARG2, cg->dword[PTR(ptr)]); // reload value for interrupt test below
if (CodeCache::IsUsingFastmem())
cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]); cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]);
SwitchToNearCode(true);
cg->L(caches_unchanged);
TestInterrupts(RWARG2); TestInterrupts(RWARG2);
} }