From 10e2079ee43f13b0338a96e73f88269fc48d956d Mon Sep 17 00:00:00 2001 From: Stenzek Date: Thu, 19 Dec 2024 18:21:59 +1000 Subject: [PATCH] CPU/Recompiler: Don't use far code for mtc0 cache check Redundant for a few instructions. --- src/core/cpu_recompiler_arm32.cpp | 8 ++++++-- src/core/cpu_recompiler_arm64.cpp | 8 +++++--- src/core/cpu_recompiler_riscv64.cpp | 8 +++++--- src/core/cpu_recompiler_x64.cpp | 9 ++++++--- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/core/cpu_recompiler_arm32.cpp b/src/core/cpu_recompiler_arm32.cpp index 2e6220ac8..03a0bf902 100644 --- a/src/core/cpu_recompiler_arm32.cpp +++ b/src/core/cpu_recompiler_arm32.cpp @@ -2265,15 +2265,19 @@ void CPU::ARM32Recompiler::Compile_mtc0(CompileFlags cf) // We could just inline the whole thing.. Flush(FLUSH_FOR_C_CALL); - SwitchToFarCodeIfBitSet(changed_bits, 16); + Label caches_unchanged; + armAsm->tst(changed_bits, 1u << 16); + armAsm->b(eq, &caches_unchanged); EmitCall(reinterpret_cast(&CPU::UpdateMemoryPointers)); armAsm->ldr(RARG1, PTR(ptr)); // reload value for interrupt test below + armAsm->bind(&caches_unchanged); + + // might need to reload fastmem base too if (CodeCache::IsUsingFastmem() && m_block->HasFlag(CodeCache::BlockFlags::ContainsLoadStoreInstructions) && IsHostRegAllocated(RMEMBASE.GetCode())) { FreeHostReg(RMEMBASE.GetCode()); } - SwitchToNearCode(true); TestInterrupts(RARG1); } diff --git a/src/core/cpu_recompiler_arm64.cpp b/src/core/cpu_recompiler_arm64.cpp index 6bfd8a1f3..a2a961ef7 100644 --- a/src/core/cpu_recompiler_arm64.cpp +++ b/src/core/cpu_recompiler_arm64.cpp @@ -2428,11 +2428,13 @@ void CPU::ARM64Recompiler::Compile_mtc0(CompileFlags cf) // We could just inline the whole thing.. Flush(FLUSH_FOR_C_CALL); - SwitchToFarCodeIfBitSet(changed_bits, 16); + Label caches_unchanged; + armAsm->tbz(changed_bits, 16, &caches_unchanged); EmitCall(reinterpret_cast(&CPU::UpdateMemoryPointers)); armAsm->ldr(RWARG1, PTR(ptr)); // reload value for interrupt test below - armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base)); - SwitchToNearCode(true); + if (CodeCache::IsUsingFastmem()) + armAsm->ldr(RMEMBASE, PTR(&g_state.fastmem_base)); + armAsm->bind(&caches_unchanged); TestInterrupts(RWARG1); } diff --git a/src/core/cpu_recompiler_riscv64.cpp b/src/core/cpu_recompiler_riscv64.cpp index f545752e8..2ac93ecb3 100644 --- a/src/core/cpu_recompiler_riscv64.cpp +++ b/src/core/cpu_recompiler_riscv64.cpp @@ -2283,13 +2283,15 @@ void CPU::RISCV64Recompiler::Compile_mtc0(CompileFlags cf) // We could just inline the whole thing.. Flush(FLUSH_FOR_C_CALL); + Label caches_unchanged; rvAsm->SRLIW(RSCRATCH, changed_bits, 16); rvAsm->ANDI(RSCRATCH, RSCRATCH, 1); - SwitchToFarCode(true, &Assembler::BEQ, RSCRATCH, zero); + rvAsm->BEQ(RSCRATCH, zero, &caches_unchanged); EmitCall(reinterpret_cast(&CPU::UpdateMemoryPointers)); rvAsm->LW(new_value, PTR(ptr)); - rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base)); - SwitchToNearCode(true); + if (CodeCache::IsUsingFastmem()) + rvAsm->LD(RMEMBASE, PTR(&g_state.fastmem_base)); + rvAsm->Bind(&caches_unchanged); TestInterrupts(RARG1); } diff --git a/src/core/cpu_recompiler_x64.cpp b/src/core/cpu_recompiler_x64.cpp index 9be9c7c21..696a214aa 100644 --- a/src/core/cpu_recompiler_x64.cpp +++ b/src/core/cpu_recompiler_x64.cpp @@ -2241,12 +2241,15 @@ void CPU::X64Recompiler::Compile_mtc0(CompileFlags cf) // We could just inline the whole thing.. Flush(FLUSH_FOR_C_CALL); + Label caches_unchanged; cg->test(changed_bits, 1u << 16); - SwitchToFarCode(true, &CodeGenerator::jnz); + cg->jz(caches_unchanged); cg->call(&CPU::UpdateMemoryPointers); cg->mov(RWARG2, cg->dword[PTR(ptr)]); // reload value for interrupt test below - cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]); - SwitchToNearCode(true); + if (CodeCache::IsUsingFastmem()) + cg->mov(RMEMBASE, cg->qword[PTR(&g_state.fastmem_base)]); + + cg->L(caches_unchanged); TestInterrupts(RWARG2); }