497 lines
17 KiB
C++
497 lines
17 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "DSPIntUtil.h"
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#include "DSPMemoryMap.h"
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#include "DSPIntExtOps.h"
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// Extended opcodes do not exist on their own. These opcodes can only be
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// attached to opcodes that allow extending (8 (or 7) lower bits of opcode not used by
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// opcode). Extended opcodes do not modify program counter $pc register.
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// Most of the suffixes increment or decrement one or more addressing registers
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// (the first four, ARx). The increment/decrement is either 1, or the
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// corresponding "index" register (the second four, IXx). The addressing
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// registers will wrap in odd ways, dictated by the corresponding wrapping
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// register, WR0-3.
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namespace DSPInterpreter
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{
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namespace Ext
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{
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inline bool IsSameMemArea(u16 a, u16 b)
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{
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//LM: tested on WII
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if ((a>>10)==(b>>10))
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return true;
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else
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return false;
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}
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// DR $arR
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// xxxx xxxx 0000 01rr
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// Decrement addressing register $arR.
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void dr(const UDSPInstruction opc) {
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writeToBackLog(0, opc & 0x3, dsp_decrement_addr_reg(opc & 0x3));
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}
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// IR $arR
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// xxxx xxxx 0000 10rr
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// Increment addressing register $arR.
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void ir(const UDSPInstruction opc) {
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writeToBackLog(0, opc & 0x3, dsp_increment_addr_reg(opc & 0x3));
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}
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// NR $arR
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// xxxx xxxx 0000 11rr
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// Add corresponding indexing register $ixR to addressing register $arR.
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void nr(const UDSPInstruction opc) {
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u8 reg = opc & 0x3;
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writeToBackLog(0, reg, dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]));
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}
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// MV $axD.D, $acS.S
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// xxxx xxxx 0001 ddss
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// Move value of $acS.S to the $axD.D.
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void mv(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x3) + DSP_REG_ACL0;
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u8 dreg = ((opc >> 2) & 0x3);
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#if 0 //more tests
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if ((sreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
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writeToBackLog(0, dreg + DSP_REG_AXL0, ((u16)dsp_get_acc_h(sreg-DSP_REG_ACM0) & 0x0080) ? 0x8000 : 0x7fff);
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else
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#endif
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writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg]);
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}
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// S @$arD, $acS.S
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// xxxx xxxx 001s s0dd
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// Store value of $acS.S in the memory pointed by register $arD.
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// Post increment register $arD.
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void s(const UDSPInstruction opc)
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{
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u8 dreg = opc & 0x3;
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u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_increment_addr_reg(dreg));
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}
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// SN @$arD, $acS.S
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// xxxx xxxx 001s s1dd
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// Store value of register $acS.S in the memory pointed by register $arD.
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// Add indexing register $ixD to register $arD.
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void sn(const UDSPInstruction opc)
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{
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u8 dreg = opc & 0x3;
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u8 sreg = ((opc >> 3) & 0x3) + DSP_REG_ACL0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
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}
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// L $axD.D, @$arS
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// xxxx xxxx 01dd d0ss
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// Load $axD.D/$acD.D with value from memory pointed by register $arS.
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// Post increment register $arS.
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void l(const UDSPInstruction opc)
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{
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u8 sreg = opc & 0x3;
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u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
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if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
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{
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
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writeToBackLog(1, dreg, val);
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writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
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writeToBackLog(3, sreg, dsp_increment_addr_reg(sreg));
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}
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else
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{
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
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writeToBackLog(1, sreg, dsp_increment_addr_reg(sreg));
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}
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}
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// LN $axD.D, @$arS
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// xxxx xxxx 01dd d0ss
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// Load $axD.D/$acD.D with value from memory pointed by register $arS.
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// Add indexing register register $ixS to register $arS.
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void ln(const UDSPInstruction opc)
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{
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u8 sreg = opc & 0x3;
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u8 dreg = ((opc >> 3) & 0x7) + DSP_REG_AXL0;
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if ((dreg >= DSP_REG_ACM0) && (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT))
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{
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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writeToBackLog(0, dreg - DSP_REG_ACM0 + DSP_REG_ACH0, (val & 0x8000) ? 0xFFFF : 0x0000);
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writeToBackLog(1, dreg, val);
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writeToBackLog(2, dreg - DSP_REG_ACM0 + DSP_REG_ACL0, 0);
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writeToBackLog(3, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
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}
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else
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{
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[sreg]));
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writeToBackLog(1, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
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}
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}
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// LS $axD.D, $acS.m
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// xxxx xxxx 10dd 000s
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// Load register $axD.D with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Increment both $ar0 and $ar3.
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void ls(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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// LSN $axD.D, $acS.m
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// xxxx xxxx 10dd 010s
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// Load register $axD.D with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and increment $ar3.
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void lsn(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// LSM $axD.D, $acS.m
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// xxxx xxxx 10dd 100s
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// Load register $axD.D with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix3 to addressing
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// register $ar3 and increment $ar0.
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void lsm(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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// LSMN $axD.D, $acS.m
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// xxxx xxxx 10dd 110s
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// Load register $axD.D with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and add corresponding indexing register $ix3 to addressing
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// register $ar3.
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void lsnm(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR3], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR0]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// SL $acS.m, $axD.D
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// xxxx xxxx 10dd 001s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $axD.D with value from memory pointed by register
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// $ar3. Increment both $ar0 and $ar3.
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void sl(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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// SLN $acS.m, $axD.D
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// xxxx xxxx 10dd 011s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $axD.D with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and increment $ar3.
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void sln(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// SLM $acS.m, $axD.D
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// xxxx xxxx 10dd 101s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $axD.D with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix3 to addressing register $ar3
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// and increment $ar0.
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void slm(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increment_addr_reg(DSP_REG_AR0));
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}
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// SLMN $acS.m, $axD.D
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// xxxx xxxx 10dd 111s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $axD.D with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and add corresponding indexing register $ix3 to addressing register $ar3.
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void slnm(const UDSPInstruction opc)
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{
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u8 sreg = (opc & 0x1) + DSP_REG_ACM0;
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u8 dreg = ((opc >> 4) & 0x3) + DSP_REG_AXL0;
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dsp_dmem_write(g_dsp.r[DSP_REG_AR0], g_dsp.r[sreg]);
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writeToBackLog(0, dreg, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(1, DSP_REG_AR3, dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
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writeToBackLog(2, DSP_REG_AR0, dsp_increase_addr_reg(DSP_REG_AR0, (s16)g_dsp.r[DSP_REG_IX0]));
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}
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// LD $ax0.d, $ax1.r, @$arS
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// xxxx xxxx 11dr 00ss
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// example for "nx'ld $AX0.L, $AX1.L, @$AR3"
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// Loads the word pointed by AR0 to AX0.H, then loads the word pointed by AR3 to AX0.L.
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// Increments AR0 and AR3.
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// If AR0 and AR3 point into the same memory page (upper 6 bits of addr are the same -> games are not doing that!)
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// then the value pointed by AR0 is loaded to BOTH AX0.H and AX0.L.
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// If AR0 points into an invalid memory page (ie 0x2000), then AX0.H keeps its old value. (not implemented yet)
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// If AR3 points into an invalid memory page, then AX0.L gets the same value as AX0.H. (not implemented yet)
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void ld(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x1;
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u8 rreg = (opc >> 4) & 0x1;
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u8 sreg = opc & 0x3;
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if (sreg != DSP_REG_AR3) {
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writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
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if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
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writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
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else
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writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
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} else {
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writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
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if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
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writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
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else
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writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
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}
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writeToBackLog(3, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
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}
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// LDN $ax0.d, $ax1.r, @$arS
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// xxxx xxxx 11dr 01ss
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void ldn(const UDSPInstruction opc)
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{
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u8 dreg = (opc >> 5) & 0x1;
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u8 rreg = (opc >> 4) & 0x1;
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u8 sreg = opc & 0x3;
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if (sreg != DSP_REG_AR3) {
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writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
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if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
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writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
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else
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writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
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writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
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} else {
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writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
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if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
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writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
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else
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writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
|
|
|
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
|
|
}
|
|
|
|
writeToBackLog(3, DSP_REG_AR3, dsp_increment_addr_reg(DSP_REG_AR3));
|
|
}
|
|
|
|
// LDM $ax0.d, $ax1.r, @$arS
|
|
// xxxx xxxx 11dr 10ss
|
|
void ldm(const UDSPInstruction opc)
|
|
{
|
|
u8 dreg = (opc >> 5) & 0x1;
|
|
u8 rreg = (opc >> 4) & 0x1;
|
|
u8 sreg = opc & 0x3;
|
|
|
|
if (sreg != DSP_REG_AR3) {
|
|
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
|
|
|
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
|
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
|
else
|
|
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
|
|
|
writeToBackLog(2, sreg, dsp_increment_addr_reg(sreg));
|
|
} else {
|
|
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
|
|
|
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
|
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
|
else
|
|
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
|
|
|
writeToBackLog(2, dreg, dsp_increment_addr_reg(dreg));
|
|
}
|
|
|
|
writeToBackLog(3, DSP_REG_AR3,
|
|
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
|
|
}
|
|
|
|
// LDNM $ax0.d, $ax1.r, @$arS
|
|
// xxxx xxxx 11dr 11ss
|
|
void ldnm(const UDSPInstruction opc)
|
|
{
|
|
u8 dreg = (opc >> 5) & 0x1;
|
|
u8 rreg = (opc >> 4) & 0x1;
|
|
u8 sreg = opc & 0x3;
|
|
|
|
if (sreg != DSP_REG_AR3) {
|
|
writeToBackLog(0, (dreg << 1) + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[sreg]));
|
|
|
|
if (IsSameMemArea(g_dsp.r[sreg], g_dsp.r[DSP_REG_AR3]))
|
|
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[sreg]));
|
|
else
|
|
writeToBackLog(1, (rreg << 1) + DSP_REG_AXL1, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
|
|
|
writeToBackLog(2, sreg, dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]));
|
|
} else {
|
|
writeToBackLog(0, rreg + DSP_REG_AXH0, dsp_dmem_read(g_dsp.r[dreg]));
|
|
|
|
if (IsSameMemArea(g_dsp.r[dreg], g_dsp.r[DSP_REG_AR3]))
|
|
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[dreg]));
|
|
else
|
|
writeToBackLog(1, rreg + DSP_REG_AXL0, dsp_dmem_read(g_dsp.r[DSP_REG_AR3]));
|
|
|
|
writeToBackLog(2, dreg, dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]));
|
|
}
|
|
|
|
writeToBackLog(3, DSP_REG_AR3,
|
|
dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX3]));
|
|
}
|
|
|
|
|
|
void nop(const UDSPInstruction opc)
|
|
{
|
|
}
|
|
|
|
} // end namespace ext
|
|
} // end namespace DSPInterpeter
|
|
|
|
|
|
// The ext ops are calculated in parallel with the actual op. That means that
|
|
// both the main op and the ext op see the same register state as input. The
|
|
// output is simple as long as the main and ext ops don't change the same
|
|
// register. If they do the output is the bitwise or of the result of both the
|
|
// main and ext ops.
|
|
|
|
// The ext op are writing their output into the backlog which is
|
|
// being applied to the real registers after the main op was executed
|
|
void applyWriteBackLog()
|
|
{
|
|
// always make sure to have an extra entry at the end w/ -1 to avoid
|
|
// infinitive loops
|
|
for (int i = 0; writeBackLogIdx[i] != -1; i++) {
|
|
dsp_op_write_reg(writeBackLogIdx[i], g_dsp.r[writeBackLogIdx[i]] | writeBackLog[i]);
|
|
// Clear back log
|
|
writeBackLogIdx[i] = -1;
|
|
}
|
|
}
|
|
|
|
// This function is being called in the main op after all input regs were read
|
|
// and before it writes into any regs. This way we can always use bitwise or to
|
|
// apply the ext command output, because if the main op didn't change the value
|
|
// then 0 | ext output = ext output and if it did then bitwise or is still the
|
|
// right thing to do
|
|
void zeroWriteBackLog()
|
|
{
|
|
// always make sure to have an extra entry at the end w/ -1 to avoid
|
|
// infinitive loops
|
|
for (int i = 0; writeBackLogIdx[i] != -1; i++) {
|
|
dsp_op_write_reg(writeBackLogIdx[i], 0);
|
|
}
|
|
}
|
|
|
|
//needed for 0x3...
|
|
//ex. corner case -> 0x3060: main opcode modifies .m, and extended .l -> .l shoudnt be zeroed because of .m write...
|
|
void zeroWriteBackLogPreserveAcc(u8 acc)
|
|
{
|
|
for (int i = 0; writeBackLogIdx[i] != -1; i++) {
|
|
|
|
// acc0
|
|
if ((acc == 0) &&
|
|
((writeBackLogIdx[i] == DSP_REG_ACL0) || (writeBackLogIdx[i] == DSP_REG_ACM0) || (writeBackLogIdx[i] == DSP_REG_ACH0)))
|
|
continue;
|
|
|
|
// acc1
|
|
if ((acc == 1) &&
|
|
((writeBackLogIdx[i] == DSP_REG_ACL1) || (writeBackLogIdx[i] == DSP_REG_ACM1) || (writeBackLogIdx[i] == DSP_REG_ACH1)))
|
|
continue;
|
|
|
|
dsp_op_write_reg(writeBackLogIdx[i], 0);
|
|
}
|
|
}
|