533 lines
14 KiB
C++
533 lines
14 KiB
C++
// Copyright (C) 2003-2009 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "Common.h"
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#include "Thread.h"
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#include "Atomic.h"
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#include "ConfigManager.h"
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#include "Core.h"
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#include "CoreTiming.h"
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#include "HW/Memmap.h"
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#include "HW/ProcessorInterface.h"
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#include "VideoBackend.h"
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#include "SWCommandProcessor.h"
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#include "ChunkFile.h"
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#include "MathUtil.h"
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bool fifoStateRun;
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// set to 0 if using in video common
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#define SW_BACKEND 1
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#if (SW_BACKEND)
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#include "OpcodeDecoder.h"
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#else
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#include "SWVideoConfig.h"
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#include "OpcodeDecoding.h"
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#include "VideoCommon.h"
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extern u8* g_pVideoData;
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#endif
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namespace SWCommandProcessor
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{
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enum
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{
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GATHER_PIPE_SIZE = 32,
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INT_CAUSE_CP = 0x800
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};
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// STATE_TO_SAVE
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// variables
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const int commandBufferSize = 1024 * 1024;
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const int maxCommandBufferWrite = commandBufferSize - GATHER_PIPE_SIZE;
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u8 commandBuffer[commandBufferSize];
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u32 readPos;
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u32 writePos;
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int et_UpdateInterrupts;
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volatile bool interruptSet;
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volatile bool interruptWaiting;
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CPReg cpreg; // shared between gfx and emulator thread
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void DoState(PointerWrap &p)
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{
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p.Do(cpreg);
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}
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// does it matter that there is no synchronization between threads during writes?
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inline void WriteLow (u32& _reg, u16 lowbits) {_reg = (_reg & 0xFFFF0000) | lowbits;}
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inline void WriteHigh(u32& _reg, u16 highbits) {_reg = (_reg & 0x0000FFFF) | ((u32)highbits << 16);}
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inline u16 ReadLow (u32 _reg) {return (u16)(_reg & 0xFFFF);}
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inline u16 ReadHigh (u32 _reg) {return (u16)(_reg >> 16);}
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void UpdateInterrupts_Wrapper(u64 userdata, int cyclesLate)
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{
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UpdateInterrupts(userdata);
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}
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inline bool AtBreakpoint()
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{
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return cpreg.ctrl.BPEnable && (cpreg.readptr == cpreg.breakpt);
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}
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void Init()
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{
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cpreg.status.Hex = 0;
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cpreg.status.CommandIdle = 1;
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cpreg.status.ReadIdle = 1;
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cpreg.ctrl.Hex = 0;
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cpreg.clear.Hex = 0;
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cpreg.bboxleft = 0;
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cpreg.bboxtop = 0;
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cpreg.bboxright = 0;
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cpreg.bboxbottom = 0;
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cpreg.token = 0;
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et_UpdateInterrupts = CoreTiming::RegisterEvent("UpdateInterrupts", UpdateInterrupts_Wrapper);
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// internal buffer position
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readPos = 0;
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writePos = 0;
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interruptSet = false;
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interruptWaiting = false;
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g_pVideoData = 0;
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g_bSkipCurrentFrame = false;
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}
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void Shutdown()
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{
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}
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void RunGpu()
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{
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bCPUThread)
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{
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// We are going to do FP math on the main thread so have to save the current state
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SaveSSEState();
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LoadDefaultSSEState();
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// run the opcode decoder
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do {
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RunBuffer();
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} while (cpreg.ctrl.GPReadEnable && !AtBreakpoint() && cpreg.readptr != cpreg.writeptr);
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LoadSSEState();
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}
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}
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void Read16(u16& _rReturnValue, const u32 _Address)
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{
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u32 regAddr = (_Address & 0xFFF) >> 1;
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DEBUG_LOG(COMMANDPROCESSOR, "(r): 0x%08x : 0x%08x", _Address, ((u16*)&cpreg)[regAddr]);
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if (regAddr < 0x20)
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_rReturnValue = ((u16*)&cpreg)[regAddr];
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else
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_rReturnValue = 0;
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}
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void Write16(const u16 _Value, const u32 _Address)
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{
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INFO_LOG(COMMANDPROCESSOR, "(write16): 0x%04x @ 0x%08x",_Value,_Address);
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switch (_Address & 0xFFF)
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{
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case STATUS_REGISTER:
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{
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ERROR_LOG(COMMANDPROCESSOR,"\t write to STATUS_REGISTER : %04x", _Value);
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}
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break;
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case CTRL_REGISTER:
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{
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cpreg.ctrl.Hex = _Value;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to CTRL_REGISTER : %04x", _Value);
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DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | CPULINK %s | BP %s || BPIntEnable %s | OvF %s | UndF %s"
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, cpreg.ctrl.GPReadEnable ? "ON" : "OFF"
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, cpreg.ctrl.GPLinkEnable ? "ON" : "OFF"
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, cpreg.ctrl.BPEnable ? "ON" : "OFF"
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, cpreg.ctrl.BreakPointIntEnable ? "ON" : "OFF"
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, cpreg.ctrl.FifoOverflowIntEnable ? "ON" : "OFF"
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, cpreg.ctrl.FifoUnderflowIntEnable ? "ON" : "OFF"
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);
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}
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break;
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case CLEAR_REGISTER:
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{
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UCPClearReg tmpClear(_Value);
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if (tmpClear.ClearFifoOverflow)
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cpreg.status.OverflowHiWatermark = 0;
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if (tmpClear.ClearFifoUnderflow)
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cpreg.status.UnderflowLoWatermark = 0;
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INFO_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x",_Value);
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}
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break;
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// Fifo Registers
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case FIFO_TOKEN_REGISTER:
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cpreg.token = _Value;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_TOKEN_REGISTER : %04x", _Value);
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break;
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case FIFO_BASE_LO:
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WriteLow ((u32 &)cpreg.fifobase, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BASE_LO. FIFO base is : %08x", cpreg.fifobase);
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break;
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case FIFO_BASE_HI:
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WriteHigh((u32 &)cpreg.fifobase, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BASE_HI. FIFO base is : %08x", cpreg.fifobase);
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break;
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case FIFO_END_LO:
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WriteLow ((u32 &)cpreg.fifoend, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_END_LO. FIFO end is : %08x", cpreg.fifoend);
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break;
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case FIFO_END_HI:
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WriteHigh((u32 &)cpreg.fifoend, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_END_HI. FIFO end is : %08x", cpreg.fifoend);
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break;
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case FIFO_WRITE_POINTER_LO:
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WriteLow ((u32 &)cpreg.writeptr, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_WRITE_POINTER_LO. write ptr is : %08x", cpreg.writeptr);
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break;
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case FIFO_WRITE_POINTER_HI:
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WriteHigh ((u32 &)cpreg.writeptr, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_WRITE_POINTER_HI. write ptr is : %08x", cpreg.writeptr);
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break;
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case FIFO_READ_POINTER_LO:
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WriteLow ((u32 &)cpreg.readptr, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_READ_POINTER_LO. read ptr is : %08x", cpreg.readptr);
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break;
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case FIFO_READ_POINTER_HI:
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WriteHigh ((u32 &)cpreg.readptr, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_READ_POINTER_HI. read ptr is : %08x", cpreg.readptr);
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break;
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case FIFO_HI_WATERMARK_LO:
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WriteLow ((u32 &)cpreg.hiwatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_HI_WATERMARK_LO. hiwatermark is : %08x", cpreg.hiwatermark);
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break;
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case FIFO_HI_WATERMARK_HI:
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WriteHigh ((u32 &)cpreg.hiwatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_HI_WATERMARK_HI. hiwatermark is : %08x", cpreg.hiwatermark);
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break;
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case FIFO_LO_WATERMARK_LO:
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WriteLow ((u32 &)cpreg.lowatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_LO_WATERMARK_LO. lowatermark is : %08x", cpreg.lowatermark);
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break;
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case FIFO_LO_WATERMARK_HI:
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WriteHigh ((u32 &)cpreg.lowatermark, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_LO_WATERMARK_HI. lowatermark is : %08x", cpreg.lowatermark);
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break;
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case FIFO_BP_LO:
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WriteLow ((u32 &)cpreg.breakpt, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BP_LO. breakpt is : %08x", cpreg.breakpt);
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break;
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case FIFO_BP_HI:
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WriteHigh ((u32 &)cpreg.breakpt, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_BP_HI. breakpt is : %08x", cpreg.breakpt);
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break;
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case FIFO_RW_DISTANCE_LO:
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WriteLow ((u32 &)cpreg.rwdistance, _Value & 0xFFE0);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_RW_DISTANCE_LO. rwdistance is : %08x", cpreg.rwdistance);
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break;
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case FIFO_RW_DISTANCE_HI:
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WriteHigh ((u32 &)cpreg.rwdistance, _Value);
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to FIFO_RW_DISTANCE_HI. rwdistance is : %08x", cpreg.rwdistance);
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break;
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}
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RunGpu();
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}
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void Read32(u32& _rReturnValue, const u32 _Address)
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{
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_rReturnValue = 0;
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_dbg_assert_msg_(COMMANDPROCESSOR, 0, "Read32 from CommandProccessor at 0x%08x", _Address);
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}
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void Write32(const u32 _Data, const u32 _Address)
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{
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_dbg_assert_msg_(COMMANDPROCESSOR, 0, "Write32 at CommandProccessor at 0x%08x", _Address);
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}
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void STACKALIGN GatherPipeBursted()
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{
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if (cpreg.ctrl.GPLinkEnable)
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{
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DEBUG_LOG(COMMANDPROCESSOR,"\t WGP burst. write thru : %08x", cpreg.writeptr);
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if (cpreg.writeptr == cpreg.fifoend)
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cpreg.writeptr = cpreg.fifobase;
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else
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cpreg.writeptr += GATHER_PIPE_SIZE;
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Common::AtomicAdd(cpreg.rwdistance, GATHER_PIPE_SIZE);
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}
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RunGpu();
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}
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void UpdateInterrupts(u64 userdata)
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{
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if (userdata)
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{
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interruptSet = true;
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INFO_LOG(COMMANDPROCESSOR,"Interrupt set");
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ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
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}
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else
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{
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interruptSet = false;
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INFO_LOG(COMMANDPROCESSOR,"Interrupt cleared");
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ProcessorInterface::SetInterrupt(INT_CAUSE_CP, false);
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}
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interruptWaiting = false;
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}
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void UpdateInterruptsFromVideoBackend(u64 userdata)
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{
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CoreTiming::ScheduleEvent_Threadsafe(0, et_UpdateInterrupts, userdata);
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}
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void ReadFifo()
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{
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bool canRead = cpreg.readptr != cpreg.writeptr && writePos < (int)maxCommandBufferWrite;
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bool atBreakpoint = AtBreakpoint();
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if (canRead && !atBreakpoint)
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{
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// read from fifo
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u8 *ptr = Memory::GetPointer(cpreg.readptr);
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int bytesRead = 0;
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do
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{
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// copy to buffer
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memcpy(&commandBuffer[writePos], ptr, GATHER_PIPE_SIZE);
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writePos += GATHER_PIPE_SIZE;
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bytesRead += GATHER_PIPE_SIZE;
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if (cpreg.readptr == cpreg.fifoend)
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{
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cpreg.readptr = cpreg.fifobase;
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ptr = Memory::GetPointer(cpreg.readptr);
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}
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else
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{
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cpreg.readptr += GATHER_PIPE_SIZE;
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ptr += GATHER_PIPE_SIZE;
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}
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canRead = cpreg.readptr != cpreg.writeptr && writePos < (int)maxCommandBufferWrite;
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atBreakpoint = AtBreakpoint();
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} while (canRead && !atBreakpoint);
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Common::AtomicAdd(cpreg.rwdistance, -bytesRead);
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}
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}
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void SetStatus()
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{
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// overflow check
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if (cpreg.rwdistance > cpreg.hiwatermark)
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cpreg.status.OverflowHiWatermark = 1;
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// underflow check
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if (cpreg.rwdistance < cpreg.lowatermark)
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cpreg.status.UnderflowLoWatermark = 1;
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// breakpoint
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if (cpreg.ctrl.BPEnable)
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{
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if (cpreg.breakpt == cpreg.readptr)
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{
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if (!cpreg.status.Breakpoint)
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INFO_LOG(COMMANDPROCESSOR, "Hit breakpoint at %x", cpreg.readptr);
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cpreg.status.Breakpoint = 1;
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}
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}
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else
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{
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if (cpreg.status.Breakpoint)
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INFO_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %x", cpreg.readptr);
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cpreg.status.Breakpoint = 0;
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}
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cpreg.status.ReadIdle = cpreg.readptr == cpreg.writeptr;
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bool bpInt = cpreg.status.Breakpoint && cpreg.ctrl.BreakPointIntEnable;
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bool ovfInt = cpreg.status.OverflowHiWatermark && cpreg.ctrl.FifoOverflowIntEnable;
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bool undfInt = cpreg.status.UnderflowLoWatermark && cpreg.ctrl.FifoUnderflowIntEnable;
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bool interrupt = bpInt || ovfInt || undfInt;
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if (interrupt != interruptSet && !interruptWaiting)
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{
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u64 userdata = interrupt?1:0;
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if (SConfig::GetInstance().m_LocalCoreStartupParameter.bCPUThread)
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{
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interruptWaiting = true;
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SWCommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
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}
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else
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SWCommandProcessor::UpdateInterrupts(userdata);
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}
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}
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bool RunBuffer()
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{
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// fifo is read 32 bytes at a time
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// read fifo data to internal buffer
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if (cpreg.ctrl.GPReadEnable)
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ReadFifo();
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SetStatus();
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_dbg_assert_(COMMANDPROCESSOR, writePos >= readPos);
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g_pVideoData = &commandBuffer[readPos];
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u32 availableBytes = writePos - readPos;
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#if (SW_BACKEND)
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while (OpcodeDecoder::CommandRunnable(availableBytes))
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{
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cpreg.status.CommandIdle = 0;
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OpcodeDecoder::Run(availableBytes);
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// if data was read by the opcode decoder then the video data pointer changed
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readPos = (u32)(g_pVideoData - &commandBuffer[0]);
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_dbg_assert_(VIDEO, writePos >= readPos);
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availableBytes = writePos - readPos;
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}
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#else
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cpreg.status.CommandIdle = 0;
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OpcodeDecoder_Run(g_bSkipCurrentFrame);
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// if data was read by the opcode decoder then the video data pointer changed
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readPos = g_pVideoData - &commandBuffer[0];
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_dbg_assert_(COMMANDPROCESSOR, writePos >= readPos);
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availableBytes = writePos - readPos;
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#endif
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cpreg.status.CommandIdle = 1;
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bool ranDecoder = false;
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// move data remaing in command buffer
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if (readPos > 0)
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{
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memmove(&commandBuffer[0], &commandBuffer[readPos], availableBytes);
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writePos -= readPos;
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readPos = 0;
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ranDecoder = true;
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}
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return ranDecoder;
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}
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} // end of namespace SWCommandProcessor
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// fifo functions
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#if (SW_BACKEND)
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void SWFifo_EnterLoop()
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{
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fifoStateRun = true;
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while (fifoStateRun)
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{
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g_video_backend->PeekMessages();
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if (!SWCommandProcessor::RunBuffer()) {
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Common::YieldCPU();
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}
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}
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}
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#else
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void Fifo_EnterLoop(const SVideoInitialize &video_initialize)
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{
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fifoStateRun = true;
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while (fifoStateRun)
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{
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g_VideoInitialize.pPeekMessages();
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if (g_ActiveConfig.bEFBAccessEnable)
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VideoFifo_CheckEFBAccess();
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VideoFifo_CheckSwapRequest();
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if (!CommandProcessor::RunBuffer()) {
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Common::YieldCPU();
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}
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}
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}
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#endif
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#if 0
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void Fifo_ExitLoop()
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{
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fifoStateRun = false;
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}
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void Fifo_SetRendering(bool enabled)
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{
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g_bSkipCurrentFrame = !enabled;
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}
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// for compatibility with video common
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void Fifo_Init() {}
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void Fifo_Shutdown() {}
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void Fifo_DoState(PointerWrap &p) {}
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u8* FAKE_GetFifoStartPtr()
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{
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return SWCommandProcessor::commandBuffer;
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}
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u8* FAKE_GetFifoEndPtr()
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{
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return &SWCommandProcessor::commandBuffer[SWCommandProcessor::writePos];
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}
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#endif
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