e9164247d6
Merge pull request #1108 from FioraAeterna/fixdebugscroll
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Debugger: scroll by multiples of 4 bytes
2014-09-18 06:52:44 -05:00
d54c8eb6bf
Merge pull request #1098 from FioraAeterna/cvtsi2ss
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JIT: use cvtsi2ss in paired singles
2014-09-18 06:51:37 -05:00
0294b344e2
Merge pull request #1086 from FioraAeterna/fixsrawint
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Interpreter: fix carry calculation in srawx
2014-09-18 06:41:37 -05:00
20c3a0f2d8
Debugger: scroll by multiples of 4 bytes
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Avoids that weird effect where scrolling offsets code from 4-byte boundaries,
showing nonsense 75% of the time.
2014-09-18 03:54:57 -07:00
8ce4676605
Debugger: make opcode search a bit better
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Search a wider range (not all games fit in the originally searched range).
Print a notice if the opcode isn't found, instead of silently failing.
2014-09-18 03:47:46 -07:00
cd7853bd50
JIT: fix debug mode
2014-09-18 03:14:04 -07:00
74eee70fad
Merge pull request #1105 from FioraAeterna/pssel
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JIT: fix regression in ps_sel
2014-09-18 14:55:47 +10:00
9ab816e6e9
JIT: fix regression in ps_sel
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My code didn't maintain correct semantics with floating-point NaNs (a < b is
not the same as "not a >= b" in float), which seems to have broken FIFA 12.
2014-09-17 21:43:44 -07:00
8b151d6a61
Merge pull request #1104 from comex/its-like-the-bad-old-days-where-i-broke-master-over-and-over
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Fix BLR optimization (sorry)
2014-09-17 19:38:28 -07:00
217758b607
Correct inaccurate comment.
2014-09-17 22:30:33 -04:00
6695b5acce
Fix backwards #ifdef.
2014-09-17 22:30:20 -04:00
97c9cb5882
Add missing push wrapper around UpdatePerformanceMonitor
2014-09-17 21:10:43 -04:00
49a48a6057
Merge pull request #1025 from comex/blr-optimization
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Opportunistically predict BLR destinations using RET.
2014-09-17 20:26:57 -04:00
29fc151cc7
JIT: implement remaining psq_l/st instruction variants
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These are used in at least a few popular games, including Super Smash Bros.
Brawl.
2014-09-17 17:10:27 -07:00
7ad9027593
Be pedantic about stack overflow on Linux and OS X.
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Add some magic to the fault handler to handle stack overflow due to BLR
optimization, and disable the optimization if fastmem is not enabled.
2014-09-17 20:08:09 -04:00
cfd65c2762
JIT: rename a few constants to be more accurate
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Remove the '2'; it's not longer applicable.
2014-09-17 16:59:35 -07:00
755bd2c445
Reorganize backpatching a bit. Untested on ARM.
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Rather than *MemTools.cpp checking whether the address is in the
emulated range itself (which, as of the next commit, doesn't cover every
kind of access the JIT might want to intercept) and doing PC
replacement, they just pass the access address and context to
jit->HandleFault, which does the rest itself.
Because SContext is now in JitInterface, I wanted JitBackpatch.h (which
defines it) to be lightweight, so I moved TrampolineCache and associated
x64{Analyzer,Emitter} dependencies into its own file. I hate adding new
files in three places, two of which are MSVC...
While I'm at it, edit a misleading comment.
2014-09-17 19:57:06 -04:00
7b0fdb52cd
Run exception handlers on an alternate stack on Linux.
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*Completely untested.* Someone please test.
2014-09-17 19:57:04 -04:00
bd4e75e69a
Shorten the blr stub a bit.
2014-09-17 19:56:58 -04:00
b597ec3e08
Opportunistically predict BLR destinations using RET.
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When executing a BL-type instruction, push the new LR onto the stack,
then CALL the dispatcher or linked block rather than JMPing to it. When
executing BLR, compare [rsp+8] to LR, and RET if it's right, which it
usually will be unless the thread was switched out. If it's not right,
reset RSP to avoid overflow.
This both saves a trip through the dispatcher and improves branch
prediction.
There is a small possibility of stack overflow anyway, which should
be handled... *yawn*
2014-09-17 19:56:09 -04:00
558dee84ca
Wrap some function calls in ABI_Push|PopRegistersAndAdjustStack(0, 0);
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These calls are made outside of JIT blocks, and thus previously did not
read any protection - register use is taken into account and the outer
dispatcher stack frame is sufficient. However, if data is to be stored
on the stack, these calls must reserve stack shadow space on Windows to
avoid clobbering it.
2014-09-17 19:56:09 -04:00
2a0b06f08c
JIT: simpler fallback conditions for load/store float
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I wasn't really thinking when I wrote these; d/s are for float registers, not
gprs.
2014-09-17 10:27:33 -07:00
5fafcb6680
Merge pull request #1099 from FioraAeterna/updatecomments
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JIT: update some rather outdated comments
2014-09-17 08:50:59 +02:00
76c8bb40e8
JIT: update some rather outdated comments
2014-09-16 23:42:22 -07:00
2ae6f13d22
JIT: use cvtsi2ss in paired singles
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One less instruction for a few of the loads.
2014-09-16 22:50:33 -07:00
978a855d3f
Merge pull request #1090 from shuffle2/dolphin-qt
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DolphinQt -- initial commit
2014-09-16 22:21:16 -07:00
2c233c4976
Merge pull request #686 from FioraAeterna/fiora
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JIT: Optimize JitAsmCommon, Float, and PS implementations
2014-09-17 14:06:14 +10:00
cdecfa3c87
Merge pull request #1094 from FioraAeterna/fixdisasm2
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GekkoDisassembler: fix some float opcodes
2014-09-17 01:52:23 +02:00
5dc88a2673
Add hotkeys to select save state slots and to save/load the currently selected slots.
2014-09-16 19:19:41 -04:00
d3dee1d7ed
GekkoDisassembler: fix some float opcodes
2014-09-16 02:06:40 -07:00
0dd05f4a3f
Merge pull request #1092 from comex/that-aint-ruby
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Fix missing "return"
2014-09-16 00:27:19 -04:00
7eea7080d9
Fix missing "return"
2014-09-16 00:25:21 -04:00
8361d2b1da
Merge pull request #805 from FioraAeterna/storerefactor
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JIT: support immediate stores
2014-09-16 13:31:39 +10:00
bef2016909
Merge pull request #1091 from FioraAeterna/fixdisasm
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GekkoDisassembler: fix/improve disassembly for a few instructions
2014-09-16 03:53:18 +02:00
7368c2ee9e
GekkoDisassembler: fix/improve disassembly for a few instructions
2014-09-15 18:48:54 -07:00
9d57ac68a4
Add Qt submodule for windows.
2014-09-15 15:07:42 -07:00
ae3a5ce9e3
Qt: Add msvc support
2014-09-15 15:07:33 -07:00
16c6a19190
DolphinQt: initial commit.
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This adds the beginning of the DolphinQt user interface. It doesn't
do anything useful yet and only builds via CMake.
2014-09-15 15:06:05 -07:00
847f78e4cc
Merge pull request #1089 from FioraAeterna/fixemittersilentfail
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x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands
2014-09-15 14:53:21 -04:00
764ce4b513
JIT: add fselx implementation
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Based on a patch by Tilka.
2014-09-15 08:33:41 -07:00
7ab820c6f8
JIT: Various JitAsmCommon optimizations
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Use some SSE4 instructions in on CPUs that support them.
Use float instructions instead of int where appropriate (it's a cycle faster
on CPUs with arithmetic unit forwarding penalties).
2014-09-15 08:33:40 -07:00
7b0f559ae1
JIT: various float optimizations
2014-09-15 08:33:40 -07:00
34287b8042
JIT: some paired singles optimizations
2014-09-15 08:33:39 -07:00
d02b7c7755
JIT: support immediate stores
2014-09-15 07:25:32 -07:00
02dce5dbbf
x64Emitter: fix silent failure if WriteNormalOp is passed two memory operands
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Should now fail loudly and clearly instead.
2014-09-15 07:08:08 -07:00
68b2d86daf
Merge pull request #1088 from FioraAeterna/revert-1077-integeropts2
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Revert "Two small JIT optimizations"
2014-09-15 09:03:16 -05:00
a248e49c97
Revert "Two small JIT optimizations"
2014-09-15 07:01:51 -07:00
20af50b1c4
Merge pull request #1077 from FioraAeterna/integeropts2
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Two small JIT optimizations
2014-09-15 07:09:11 -05:00
1458b59156
Merge pull request #1065 from Sonicadvance1/AArch64-fix-regcache
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Fix all the current issues with the AArch64 register cache.
2014-09-15 13:02:16 +10:00
3845c27155
JIT: save an instruction in psq_l
2014-09-14 15:12:57 -07:00
Ryan Houdek