JIT: support immediate stores
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68b2d86daf
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d02b7c7755
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@ -136,6 +136,7 @@ bool DisassembleMov(const unsigned char *codePtr, InstructionInfo *info)
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info->isMemoryWrite = true;
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info->hasImmediate = true;
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info->immediate = *codePtr;
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info->operandSize = 1;
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codePtr++;
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break;
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@ -399,18 +399,25 @@ void Jit64::stX(UGeckoInstruction inst)
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gpr.Lock(a, s);
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gpr.BindToRegister(a, true, false);
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X64Reg reg_value;
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if (WriteClobbersRegValue(accessSize, /* swap */ true))
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if (gpr.R(s).IsImm())
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{
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MOV(32, R(RSCRATCH2), gpr.R(s));
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reg_value = RSCRATCH2;
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SafeWriteRegToReg(gpr.R(s), gpr.RX(a), accessSize, offset, CallerSavedRegistersInUse(), SAFE_LOADSTORE_CLOBBER_RSCRATCH_INSTEAD_OF_ADDR);
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}
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else
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{
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gpr.BindToRegister(s, true, false);
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reg_value = gpr.RX(s);
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X64Reg reg_value;
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if (WriteClobbersRegValue(accessSize, /* swap */ true))
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{
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MOV(32, R(RSCRATCH2), gpr.R(s));
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reg_value = RSCRATCH2;
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}
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else
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{
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gpr.BindToRegister(s, true, false);
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reg_value = gpr.RX(s);
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}
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SafeWriteRegToReg(reg_value, gpr.RX(a), accessSize, offset, CallerSavedRegistersInUse(), SAFE_LOADSTORE_CLOBBER_RSCRATCH_INSTEAD_OF_ADDR);
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}
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SafeWriteRegToReg(reg_value, gpr.RX(a), accessSize, offset, CallerSavedRegistersInUse(), SAFE_LOADSTORE_CLOBBER_RSCRATCH_INSTEAD_OF_ADDR);
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if (update && offset)
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{
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@ -474,18 +481,25 @@ void Jit64::stXx(UGeckoInstruction inst)
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break;
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}
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X64Reg reg_value;
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if (WriteClobbersRegValue(accessSize, /* swap */ true))
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if (gpr.R(s).IsImm())
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{
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MOV(32, R(RSCRATCH), gpr.R(s));
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reg_value = RSCRATCH;
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SafeWriteRegToReg(gpr.R(s), RSCRATCH2, accessSize, 0, CallerSavedRegistersInUse());
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}
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else
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{
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gpr.BindToRegister(s, true, false);
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reg_value = gpr.RX(s);
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X64Reg reg_value;
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if (WriteClobbersRegValue(accessSize, /* swap */ true))
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{
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MOV(32, R(RSCRATCH), gpr.R(s));
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reg_value = RSCRATCH;
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}
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else
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{
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gpr.BindToRegister(s, true, false);
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reg_value = gpr.RX(s);
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}
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SafeWriteRegToReg(reg_value, RSCRATCH2, accessSize, 0, CallerSavedRegistersInUse());
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}
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SafeWriteRegToReg(reg_value, RSCRATCH2, accessSize, 0, CallerSavedRegistersInUse());
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if (update && js.memcheck)
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{
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@ -530,8 +544,15 @@ void Jit64::stmw(UGeckoInstruction inst)
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MOV(32, R(RSCRATCH), gpr.R(inst.RA));
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else
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XOR(32, R(RSCRATCH), R(RSCRATCH));
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MOV(32, R(RSCRATCH2), gpr.R(i));
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SafeWriteRegToReg(RSCRATCH2, RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16, CallerSavedRegistersInUse());
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if (gpr.R(i).IsImm())
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{
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SafeWriteRegToReg(gpr.R(i), RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16, CallerSavedRegistersInUse());
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}
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else
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{
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MOV(32, R(RSCRATCH2), gpr.R(i));
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SafeWriteRegToReg(RSCRATCH2, RSCRATCH, 32, (i - inst.RD) * 4 + (u32)(s32)inst.SIMM_16, CallerSavedRegistersInUse());
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}
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}
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gpr.UnlockAllX();
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}
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@ -115,8 +115,31 @@ const u8 *TrampolineCache::GetWriteTrampoline(const InstructionInfo &info, u32 r
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ABI_PushRegistersAndAdjustStack(registersInUse, 8);
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MOVTwo(64, ABI_PARAM1, dataReg, ABI_PARAM2, addrReg);
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if (info.hasImmediate)
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{
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if (addrReg != ABI_PARAM2)
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MOV(64, R(ABI_PARAM2), R(addrReg));
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// we have to swap back the immediate to pass it to the write functions
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switch (info.operandSize)
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{
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case 8:
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PanicAlert("Invalid 64-bit immediate!");
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break;
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case 4:
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MOV(32, R(ABI_PARAM1), Imm32(Common::swap32((u32)info.immediate)));
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break;
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case 2:
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MOV(16, R(ABI_PARAM1), Imm16(Common::swap16((u16)info.immediate)));
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break;
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case 1:
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MOV(8, R(ABI_PARAM1), Imm8((u8)info.immediate));
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break;
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}
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}
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else
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{
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MOVTwo(64, ABI_PARAM1, dataReg, ABI_PARAM2, addrReg);
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}
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if (info.displacement)
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{
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ADD(32, R(ABI_PARAM2), Imm32(info.displacement));
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@ -220,7 +243,7 @@ const u8 *Jitx86Base::BackPatch(u8 *codePtr, u32 emAddress, void *ctx_void)
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u32 pc = it->second;
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u8 *start;
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if (info.byteSwap)
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if (info.byteSwap || info.hasImmediate)
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{
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// The instruction is a MOVBE but it failed so the value is still in little-endian byte order.
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start = codePtr;
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@ -250,10 +250,11 @@ void EmuCodeBlock::MMIOLoadToReg(MMIO::Mapping* mmio, Gen::X64Reg reg_value,
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}
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}
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FixupBranch EmuCodeBlock::CheckIfSafeAddress(X64Reg reg_value, X64Reg reg_addr, u32 registers_in_use, u32 mem_mask)
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FixupBranch EmuCodeBlock::CheckIfSafeAddress(OpArg reg_value, X64Reg reg_addr, u32 registers_in_use, u32 mem_mask)
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{
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registers_in_use |= (1 << reg_addr);
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registers_in_use |= (1 << reg_value);
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if (reg_value.IsSimpleReg())
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registers_in_use |= (1 << reg_value.GetSimpleReg());
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// Get ourselves a free register; try to pick one that doesn't involve pushing, if we can.
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X64Reg scratch = RSCRATCH;
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@ -381,7 +382,7 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg & opAddress,
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}
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FixupBranch slow, exit;
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slow = CheckIfSafeAddress(reg_value, reg_addr, registersInUse, mem_mask);
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slow = CheckIfSafeAddress(R(reg_value), reg_addr, registersInUse, mem_mask);
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UnsafeLoadToReg(reg_value, R(reg_addr), accessSize, 0, signExtend);
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if (farcode.Enabled())
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SwitchToFarCode();
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@ -429,34 +430,55 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg & opAddress,
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}
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}
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u8 *EmuCodeBlock::UnsafeWriteRegToReg(X64Reg reg_value, X64Reg reg_addr, int accessSize, s32 offset, bool swap)
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u8 *EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset, bool swap)
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{
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u8* result = GetWritableCodePtr();
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OpArg dest = MComplex(RMEM, reg_addr, SCALE_1, offset);
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if (swap)
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if (reg_value.IsImm())
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{
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if (swap)
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{
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if (accessSize == 32)
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reg_value = Imm32(Common::swap32((u32)reg_value.offset));
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else if (accessSize == 16)
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reg_value = Imm16(Common::swap16((u16)reg_value.offset));
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else
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reg_value = Imm8((u8)reg_value.offset);
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}
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MOV(accessSize, dest, reg_value);
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}
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else if (swap)
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(accessSize, dest, R(reg_value));
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MOVBE(accessSize, dest, reg_value);
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}
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else
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{
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if (accessSize > 8)
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BSWAP(accessSize, reg_value);
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BSWAP(accessSize, reg_value.GetSimpleReg());
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result = GetWritableCodePtr();
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MOV(accessSize, dest, R(reg_value));
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MOV(accessSize, dest, reg_value);
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}
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}
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else
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{
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MOV(accessSize, dest, R(reg_value));
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MOV(accessSize, dest, reg_value);
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}
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return result;
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}
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void EmuCodeBlock::SafeWriteRegToReg(X64Reg reg_value, X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags)
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void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags)
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{
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// set the correct immediate format
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if (reg_value.IsImm())
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{
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reg_value = accessSize == 32 ? Imm32((u32)reg_value.offset) :
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accessSize == 16 ? Imm16((u16)reg_value.offset) :
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Imm8((u8)reg_value.offset);
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}
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU &&
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SConfig::GetInstance().m_LocalCoreStartupParameter.bFastmem &&
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!(flags & (SAFE_LOADSTORE_NO_SWAP | SAFE_LOADSTORE_NO_FASTMEM))
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@ -515,24 +537,38 @@ void EmuCodeBlock::SafeWriteRegToReg(X64Reg reg_value, X64Reg reg_addr, int acce
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else
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exit = J(true);
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SetJumpTarget(slow);
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// PC is used by memory watchpoints (if enabled) or to print accurate PC locations in debug logs
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MOV(32, PPCSTATE(pc), Imm32(jit->js.compilerPC));
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size_t rsp_alignment = (flags & SAFE_LOADSTORE_NO_PROLOG) ? 8 : 0;
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ABI_PushRegistersAndAdjustStack(registersInUse, rsp_alignment);
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// If the input is an immediate, we need to put it in a register.
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X64Reg reg;
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if (reg_value.IsImm())
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{
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reg = reg_addr == ABI_PARAM1 ? RSCRATCH : ABI_PARAM1;
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MOV(accessSize, R(reg), reg_value);
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}
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else
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{
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reg = reg_value.GetSimpleReg();
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}
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switch (accessSize)
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{
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case 64:
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U64) : ((void *)&Memory::Write_U64_Swap), reg_value, reg_addr);
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U64) : ((void *)&Memory::Write_U64_Swap), reg, reg_addr);
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break;
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case 32:
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U32) : ((void *)&Memory::Write_U32_Swap), reg_value, reg_addr);
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U32) : ((void *)&Memory::Write_U32_Swap), reg, reg_addr);
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break;
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case 16:
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U16) : ((void *)&Memory::Write_U16_Swap), reg_value, reg_addr);
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ABI_CallFunctionRR(swap ? ((void *)&Memory::Write_U16) : ((void *)&Memory::Write_U16_Swap), reg, reg_addr);
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break;
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case 8:
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ABI_CallFunctionRR((void *)&Memory::Write_U8, reg_value, reg_addr);
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ABI_CallFunctionRR((void *)&Memory::Write_U8, reg, reg_addr);
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break;
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}
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ABI_PopRegistersAndAdjustStack(registersInUse, rsp_alignment);
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@ -76,11 +76,15 @@ public:
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void LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src);
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void SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src);
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Gen::FixupBranch CheckIfSafeAddress(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, u32 registers_in_use, u32 mem_mask);
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Gen::FixupBranch CheckIfSafeAddress(Gen::OpArg reg_value, Gen::X64Reg reg_addr, u32 registers_in_use, u32 mem_mask);
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void UnsafeLoadRegToReg(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize, s32 offset = 0, bool signExtend = false);
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void UnsafeLoadRegToRegNoSwap(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize, s32 offset, bool signExtend = false);
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// these return the address of the MOV, for backpatching
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u8 *UnsafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset = 0, bool swap = true);
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u8 *UnsafeWriteRegToReg(Gen::OpArg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset = 0, bool swap = true);
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u8 *UnsafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset = 0, bool swap = true)
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{
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UnsafeWriteRegToReg(R(reg_value), reg_addr, accessSize, offset, swap);
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}
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u8 *UnsafeLoadToReg(Gen::X64Reg reg_value, Gen::OpArg opAddress, int accessSize, s32 offset, bool signExtend);
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// Generate a load/write from the MMIO handler for a given address. Only
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@ -98,7 +102,12 @@ public:
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void SafeLoadToReg(Gen::X64Reg reg_value, const Gen::OpArg & opAddress, int accessSize, s32 offset, u32 registersInUse, bool signExtend, int flags = 0);
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// Clobbers RSCRATCH or reg_addr depending on the relevant flag. Preserves
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// reg_value if the load fails and js.memcheck is enabled.
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void SafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags = 0);
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// Works with immediate inputs and simple registers only.
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void SafeWriteRegToReg(Gen::OpArg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags = 0);
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void SafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset, u32 registersInUse, int flags = 0)
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{
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SafeWriteRegToReg(R(reg_value), reg_addr, accessSize, offset, registersInUse, flags);
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}
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// applies to safe and unsafe WriteRegToReg
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bool WriteClobbersRegValue(int accessSize, bool swap)
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