Commit Graph

23 Commits

Author SHA1 Message Date
Ryan Houdek f1a9db9bdc [AArch64] Stop violating the AAPCS64 so much. 2015-03-02 11:21:15 -06:00
Ryan Houdek 39e357d62d [AArch64] Implement VFP loadstore paired in the emitter. 2015-03-02 06:27:17 -06:00
Ryan Houdek 8b8310d28c [AArch64] Optimize FPR pushing and popping.
Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.

On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
2015-03-02 06:27:13 -06:00
Ryan Houdek 120df4c688 [AArch64] Implement loadstore unscaled. 2015-02-16 22:00:43 -06:00
Ryan Houdek 814aaaf538 [AArch64] Implement a couple of emitter instructions.
These will be used with the vertex loader JIT recompiler.
2015-02-13 12:16:06 -06:00
Ryan Houdek 0252bbb33f [AArch64] Fix non-PCH build. 2015-02-13 12:16:05 -06:00
Ryan Houdek 8074d06270 [ARM] Fix poison memory functions.
We were poisoning 4x more data and overrunning our buffers. We don't want to do this.
2015-02-13 12:16:05 -06:00
Ryan Houdek 8c53b88cc3 [AArch64] Implement a way to call lambdas in the emitter 2015-01-29 01:50:11 -06:00
Ryan Houdek 6470227a39 [AArch64] Minor fix in the UMULH/SMULH.
These two instructions ignore the register encoded in to RA.
2015-01-22 18:08:49 -06:00
Ryan Houdek 217c2c9d6a [AArch64] Add some more scalar VFP ops to the emitter. 2015-01-20 16:34:32 -06:00
Ryan Houdek 8d5947efac [AArch64] Emitter improvements.
Adds a bunch of new instructions to the emitter.
2015-01-18 16:25:40 -06:00
Ryan Houdek c511ee763a [AArch64] Add the float emitter. 2015-01-08 19:55:31 -06:00
Ryan Houdek 5a0133c478 [AArch64] Add a few more VFP register helpers.
Renames Is128Bit to IsQuad to line up more with the other helpers.
2015-01-07 13:05:55 -06:00
Ryan Houdek 2b4f1aed40 [AArch64] Minor shifted register adjustment.
If we have a shift amount that is the full length of the source register then we have an invalid instruction.
This can happen when dealing with a couple of PowerPC instructions.
This same adjustment is already in the ARMv7 emitter.
2015-01-07 13:03:51 -06:00
Ryan Houdek 0a23ca9461 [AArch64] Add MUL/MNEG instruction aliases to the emitter. 2015-01-07 13:03:01 -06:00
Ryan Houdek 8dba84dd7c [AArch64] Fix 8 & 16 bit loadstore indexes.
I wasn't bit shifting correctly for 8 and 16bit loadstores.
2015-01-07 12:58:37 -06:00
Ryan Houdek d3c2e8fb0a [AArch64] Improvements to the AArch64 emitter.
Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
2014-12-20 19:35:52 -06:00
Ryan Houdek 2c39d4044d [AArch64] Add loadstore paired emitter instructions. 2014-12-02 21:08:34 -06:00
Ryan Houdek 7608e3f11e Add AArch64 emitter aliases for MOV and MVN. 2014-09-18 16:30:40 -05:00
Lioncash a92003c1ab ARM64: Make getters within ArithOption const. 2014-09-12 20:55:26 -04:00
Ryan Houdek 24f6c98a55 Add sign extending aliases to the ARM64Emitter. 2014-09-10 17:52:54 -05:00
Lioncash bc331ee809 Common: Fix code styling in Arm64Emitter 2014-09-08 23:39:20 -04:00
Ryan Houdek f107b5e176 [AArch64-emitter] Initial work on a emitter for 64bit ARM.
I've tested a few instruction encodings and am expecting most to work as long as one stays away from VFP/SIMD.
This implements mostly instructions to bring up an initial JIT with integer support.
This can be improved to allow ease of use functions in the future, dealing with the raw imms/immr encodings is probably the worst thing ever.
2014-09-06 20:13:44 -05:00