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1 Commits

Author SHA1 Message Date
Pokechu22 14119c86a4 DSPInterpreter: Fix IsLess
`IsLess` would incorrectly return true if both `SR_OVERFLOW` and `SR_SIGN` are set, as `(sr & SR_OVERFLOW) != (sr & SR_SIGN)` becomes `SR_OVERFLOW != SR_SIGN` which is true as the two masks are different.  This broke in e651592ef5.

This issue only affected the DSP LLE Interpreter, and not the DSP LLE JIT.

I've also included a simple test case for this.  `ax0.l` (on the top left) is set to 0 if the instruction following `IFL` does not execute and to 1 if it is executed.
2021-08-15 19:45:44 -07:00