ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

DSPInterpreter: Fix IsLess 

`IsLess` would incorrectly return true if both `SR_OVERFLOW` and `SR_SIGN` are set, as `(sr & SR_OVERFLOW) != (sr & SR_SIGN)` becomes `SR_OVERFLOW != SR_SIGN` which is true as the two masks are different.  This broke in e651592ef5.

This issue only affected the DSP LLE Interpreter, and not the DSP LLE JIT.

I've also included a simple test case for this.  `ax0.l` (on the top left) is set to 0 if the instruction following `IFL` does not execute and to 1 if it is executed.
This commit is contained in:
Pokechu22 2021-08-15 17:00:00 -07:00
parent 4c179fe448
commit 14119c86a4
2 changed files with 17 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp
View File

@ -250,10 +250,7 @@ bool Interpreter::CheckCondition(u8 condition) const
const auto IsCarry = [this] { return IsSRFlagSet(SR_CARRY); };
const auto IsOverflow = [this] { return IsSRFlagSet(SR_OVERFLOW); };
const auto IsOverS32 = [this] { return IsSRFlagSet(SR_OVER_S32); };
const auto IsLess = [this] {
const auto& state = m_dsp_core.DSPState();
return (state.r.sr & SR_OVERFLOW) != (state.r.sr & SR_SIGN);
};
const auto IsLess = [this] { return IsSRFlagSet(SR_OVERFLOW) != IsSRFlagSet(SR_SIGN); };
const auto IsZero = [this] { return IsSRFlagSet(SR_ARITH_ZERO); };
const auto IsLogicZero = [this] { return IsSRFlagSet(SR_LOGIC_ZERO); };
const auto IsConditionA = [this] {

16
Source/DSPSpy/tests/less_test.ds Normal file
View File

@ -0,0 +1,16 @@
incdir "tests"
include "dsp_base.inc"
CLR $acc0
CLR $acc1
LRI $ac0.h, #0x0050
LRI $ac1.h, #0x0050
ADD $acc0, $acc1 ; Causes acc0 to overflow, and thus also become negative
LRI $AX0.L, #0x0000
IFL
LRI $AX0.L, #0x0001
CALL send_back
; We're done, DO NOT DELETE THIS LINE
JMP end_of_test