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JitArm64_RegCache: Make FlushMode an enum class 

Prevents namespace pollution and makes the enum members strongly typed.
This also mirrors the x64 variant as well.
This commit is contained in:
Lioncash 2020-12-30 09:26:25 -05:00
parent 8a3b14d7dc
commit fe54226575
5 changed files with 44 additions and 44 deletions
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32
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
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@ -144,8 +144,8 @@ void JitArm64::Shutdown()
void JitArm64::FallBackToInterpreter(UGeckoInstruction inst) void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
{ {
FlushCarry(); FlushCarry();
gpr.Flush(FlushMode::FLUSH_ALL, js.op); gpr.Flush(FlushMode::All, js.op);
fpr.Flush(FlushMode::FLUSH_ALL, js.op); fpr.Flush(FlushMode::All, js.op);
if (js.op->opinfo->flags & FL_ENDBLOCK) if (js.op->opinfo->flags & FL_ENDBLOCK)
{ {
@ -198,8 +198,8 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
SwitchToFarCode(); SwitchToFarCode();
SetJumpTarget(handleException); SetJumpTarget(handleException);
gpr.Flush(FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
WriteExceptionExit(js.compilerPC); WriteExceptionExit(js.compilerPC);
@ -212,8 +212,8 @@ void JitArm64::FallBackToInterpreter(UGeckoInstruction inst)
void JitArm64::HLEFunction(u32 hook_index) void JitArm64::HLEFunction(u32 hook_index)
{ {
FlushCarry(); FlushCarry();
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
MOVI2R(W0, js.compilerPC); MOVI2R(W0, js.compilerPC);
MOVI2R(W1, hook_index); MOVI2R(W1, hook_index);
@ -731,8 +731,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
TST(W30, 23, 2); TST(W30, 23, 2);
B(CC_EQ, done_here); B(CC_EQ, done_here);
gpr.Flush(FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
WriteExceptionExit(js.compilerPC, true); WriteExceptionExit(js.compilerPC, true);
SwitchToNearCode(); SwitchToNearCode();
SetJumpTarget(exit); SetJumpTarget(exit);
@ -763,8 +763,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
B(CC_EQ, done_here); B(CC_EQ, done_here);
gpr.Unlock(WA); gpr.Unlock(WA);
gpr.Flush(FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
WriteExceptionExit(js.compilerPC, true); WriteExceptionExit(js.compilerPC, true);
SwitchToNearCode(); SwitchToNearCode();
SetJumpTarget(NoExtException); SetJumpTarget(NoExtException);
@ -787,8 +787,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
SwitchToFarCode(); SwitchToFarCode();
SetJumpTarget(far_addr); SetJumpTarget(far_addr);
gpr.Flush(FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, 26, 0); // EXCEPTION_FPU_UNAVAILABLE ORR(WA, WA, 26, 0); // EXCEPTION_FPU_UNAVAILABLE
@ -807,8 +807,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
if (SConfig::GetInstance().bJITRegisterCacheOff) if (SConfig::GetInstance().bJITRegisterCacheOff)
{ {
gpr.Flush(FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FLUSH_ALL); fpr.Flush(FlushMode::All);
FlushCarry(); FlushCarry();
} }
@ -833,8 +833,8 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
if (code_block.m_broken) if (code_block.m_broken)
{ {
gpr.Flush(FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FLUSH_ALL); fpr.Flush(FlushMode::All);
WriteExit(nextPC); WriteExit(nextPC);
} }

32
Source/Core/Core/PowerPC/JitArm64/JitArm64_Branch.cpp
View File

@ -19,8 +19,8 @@ void JitArm64::sc(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITBranchOff); JITDISABLE(bJITBranchOff);
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
@ -38,8 +38,8 @@ void JitArm64::rfi(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITBranchOff); JITDISABLE(bJITBranchOff);
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
// See Interpreter rfi for details // See Interpreter rfi for details
const u32 mask = 0x87C0FFFF; const u32 mask = 0x87C0FFFF;
@ -96,8 +96,8 @@ void JitArm64::bx(UGeckoInstruction inst)
return; return;
} }
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
if (js.op->branchIsIdleLoop) if (js.op->branchIsIdleLoop)
{ {
@ -154,8 +154,8 @@ void JitArm64::bcx(UGeckoInstruction inst)
} }
gpr.Unlock(WA); gpr.Unlock(WA);
gpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
if (js.op->branchIsIdleLoop) if (js.op->branchIsIdleLoop)
{ {
@ -183,8 +183,8 @@ void JitArm64::bcx(UGeckoInstruction inst)
if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE)) if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{ {
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
WriteExit(js.compilerPC + 4); WriteExit(js.compilerPC + 4);
} }
} }
@ -206,8 +206,8 @@ void JitArm64::bcctrx(UGeckoInstruction inst)
// BO_2 == 1z1zz -> b always // BO_2 == 1z1zz -> b always
// NPC = CTR & 0xfffffffc; // NPC = CTR & 0xfffffffc;
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
if (inst.LK_3) if (inst.LK_3)
{ {
@ -275,8 +275,8 @@ void JitArm64::bclrx(UGeckoInstruction inst)
gpr.Unlock(WB); gpr.Unlock(WB);
} }
gpr.Flush(conditional ? FlushMode::FLUSH_MAINTAIN_STATE : FlushMode::FLUSH_ALL); gpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All);
fpr.Flush(conditional ? FlushMode::FLUSH_MAINTAIN_STATE : FlushMode::FLUSH_ALL); fpr.Flush(conditional ? FlushMode::MaintainState : FlushMode::All);
if (js.op->branchIsIdleLoop) if (js.op->branchIsIdleLoop)
{ {
@ -305,8 +305,8 @@ void JitArm64::bclrx(UGeckoInstruction inst)
if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE)) if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{ {
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
WriteExit(js.compilerPC + 4); WriteExit(js.compilerPC + 4);
} }
} }

6
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
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@ -239,8 +239,8 @@ void Arm64GPRCache::FlushCRRegisters(BitSet32 regs, bool maintain_state)
void Arm64GPRCache::Flush(FlushMode mode, PPCAnalyst::CodeOp* op) void Arm64GPRCache::Flush(FlushMode mode, PPCAnalyst::CodeOp* op)
{ {
FlushRegisters(BitSet32(~0U), mode == FLUSH_MAINTAIN_STATE); FlushRegisters(BitSet32(~0U), mode == FlushMode::MaintainState);
FlushCRRegisters(BitSet32(~0U), mode == FLUSH_MAINTAIN_STATE); FlushCRRegisters(BitSet32(~0U), mode == FlushMode::MaintainState);
} }
ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg) ARM64Reg Arm64GPRCache::R(const GuestRegInfo& guest_reg)
@ -391,7 +391,7 @@ void Arm64FPRCache::Flush(FlushMode mode, PPCAnalyst::CodeOp* op)
{ {
// XXX: Determine if we can keep a register in the lower 64bits // XXX: Determine if we can keep a register in the lower 64bits
// Which will allow it to be callee saved. // Which will allow it to be callee saved.
FlushRegister(i, mode == FLUSH_MAINTAIN_STATE); FlushRegister(i, mode == FlushMode::MaintainState);
} }
} }
} }

6
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
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@ -42,13 +42,13 @@ enum RegType
REG_DUP_SINGLE, // The lower one contains both registers, as single REG_DUP_SINGLE, // The lower one contains both registers, as single
}; };
enum FlushMode enum class FlushMode
{ {
// Flushes all registers, no exceptions // Flushes all registers, no exceptions
FLUSH_ALL = 0, All,
// Flushes registers in a conditional branch // Flushes registers in a conditional branch
// Doesn't wipe the state of the registers from the cache // Doesn't wipe the state of the registers from the cache
FLUSH_MAINTAIN_STATE, MaintainState,
}; };
class OpArg class OpArg

12
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
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@ -44,8 +44,8 @@ void JitArm64::mtmsr(UGeckoInstruction inst)
gpr.BindToRegister(inst.RS, true); gpr.BindToRegister(inst.RS, true);
STR(INDEX_UNSIGNED, gpr.R(inst.RS), PPC_REG, PPCSTATE_OFF(msr)); STR(INDEX_UNSIGNED, gpr.R(inst.RS), PPC_REG, PPCSTATE_OFF(msr));
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
// Our jit cache also stores some MSR bits, as they have changed, we either // Our jit cache also stores some MSR bits, as they have changed, we either
// have to validate them in the BLR/RET check, or just flush the stack here. // have to validate them in the BLR/RET check, or just flush the stack here.
@ -201,8 +201,8 @@ void JitArm64::twx(UGeckoInstruction inst)
SwitchToFarCode(); SwitchToFarCode();
SetJumpTarget(far_addr); SetJumpTarget(far_addr);
gpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE); gpr.Flush(FlushMode::MaintainState);
fpr.Flush(FlushMode::FLUSH_MAINTAIN_STATE); fpr.Flush(FlushMode::MaintainState);
LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, 24, 0); // Same as WA | EXCEPTION_PROGRAM ORR(WA, WA, 24, 0); // Same as WA | EXCEPTION_PROGRAM
@ -217,8 +217,8 @@ void JitArm64::twx(UGeckoInstruction inst)
if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE)) if (!analyzer.HasOption(PPCAnalyst::PPCAnalyzer::OPTION_CONDITIONAL_CONTINUE))
{ {
gpr.Flush(FlushMode::FLUSH_ALL); gpr.Flush(FlushMode::All);
fpr.Flush(FlushMode::FLUSH_ALL); fpr.Flush(FlushMode::All);
WriteExit(js.compilerPC + 4); WriteExit(js.compilerPC + 4);
} }
} }