Merge pull request #11289 from AdmiralCurtiss/mmu-msi-ir
MMU: Use MSR.IR for Host instruction reads.
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commit
fb0934de71
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@ -85,12 +85,12 @@ MMU::~MMU() = default;
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return Common::swap64(val);
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}
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static bool IsOpcodeFlag(XCheckTLBFlag flag)
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static constexpr bool IsOpcodeFlag(XCheckTLBFlag flag)
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{
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return flag == XCheckTLBFlag::Opcode || flag == XCheckTLBFlag::OpcodeNoException;
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}
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static bool IsNoExceptionFlag(XCheckTLBFlag flag)
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static constexpr bool IsNoExceptionFlag(XCheckTLBFlag flag)
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{
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return flag == XCheckTLBFlag::NoException || flag == XCheckTLBFlag::OpcodeNoException;
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}
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@ -148,6 +148,12 @@ static void EFB_Write(u32 data, u32 addr)
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template <XCheckTLBFlag flag, typename T, bool never_translate>
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T MMU::ReadFromHardware(u32 em_address)
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{
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// ReadFromHardware is currently used with XCheckTLBFlag::OpcodeNoException by host instruction
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// functions. Actual instruction decoding (which can raise exceptions and uses icache) is handled
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// by TryReadInstruction.
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static_assert(flag == XCheckTLBFlag::NoException || flag == XCheckTLBFlag::Read ||
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flag == XCheckTLBFlag::OpcodeNoException);
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const u32 em_address_start_page = em_address & ~HW_PAGE_MASK;
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const u32 em_address_end_page = (em_address + sizeof(T) - 1) & ~HW_PAGE_MASK;
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if (em_address_start_page != em_address_end_page)
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@ -166,7 +172,8 @@ T MMU::ReadFromHardware(u32 em_address)
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bool wi = false;
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if (!never_translate && m_ppc_state.msr.DR)
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if (!never_translate &&
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(IsOpcodeFlag(flag) ? m_ppc_state.msr.IR.Value() : m_ppc_state.msr.DR.Value()))
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{
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auto translated_addr = TranslateAddress<flag>(em_address);
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if (!translated_addr.Success())
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@ -258,6 +265,8 @@ T MMU::ReadFromHardware(u32 em_address)
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template <XCheckTLBFlag flag, bool never_translate>
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void MMU::WriteToHardware(u32 em_address, const u32 data, const u32 size)
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{
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static_assert(flag == XCheckTLBFlag::NoException || flag == XCheckTLBFlag::Write);
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DEBUG_ASSERT(size <= 4);
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const u32 em_address_start_page = em_address & ~HW_PAGE_MASK;
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@ -508,7 +517,7 @@ std::optional<ReadResult<u32>> MMU::HostTryReadInstruction(const Core::CPUThread
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case RequestedAddressSpace::Effective:
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{
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const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address);
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return ReadResult<u32>(!!mmu.m_ppc_state.msr.DR, value);
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return ReadResult<u32>(!!mmu.m_ppc_state.msr.IR, value);
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}
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case RequestedAddressSpace::Physical:
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{
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@ -517,7 +526,7 @@ std::optional<ReadResult<u32>> MMU::HostTryReadInstruction(const Core::CPUThread
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}
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case RequestedAddressSpace::Virtual:
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{
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if (!mmu.m_ppc_state.msr.DR)
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if (!mmu.m_ppc_state.msr.IR)
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return std::nullopt;
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const u32 value = mmu.ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(address);
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return ReadResult<u32>(true, value);
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@ -1464,11 +1473,13 @@ MMU::TranslateAddressResult MMU::TranslatePageAddress(const EffectiveAddress add
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for (int i = 0; i < 8; i++, pteg_addr += 8)
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{
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const u32 pteg = ReadFromHardware<flag, u32, true>(pteg_addr);
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constexpr XCheckTLBFlag pte_read_flag =
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IsNoExceptionFlag(flag) ? XCheckTLBFlag::NoException : XCheckTLBFlag::Read;
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const u32 pteg = ReadFromHardware<pte_read_flag, u32, true>(pteg_addr);
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if (pte1.Hex == pteg)
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{
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UPTE_Hi pte2(ReadFromHardware<flag, u32, true>(pteg_addr + 4));
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UPTE_Hi pte2(ReadFromHardware<pte_read_flag, u32, true>(pteg_addr + 4));
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// set the access bits
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switch (flag)
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