[AArch64] Fix ADDS/SUBS emitter functions.
These weren't emitting the flag bit. So they were regular ADD and SUB emitters.
This commit is contained in:
parent
c6e2449bff
commit
f4f59ea71e
|
@ -799,7 +799,7 @@ void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Optio
|
||||||
|
|
||||||
void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
|
void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
|
||||||
{
|
{
|
||||||
ADD(Rd, Rn, Rm, ArithOption(Rd));
|
EncodeArithmeticInst(0, true, Rd, Rn, Rm, ArithOption(Rd));
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
|
void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
|
||||||
|
@ -819,7 +819,7 @@ void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Optio
|
||||||
|
|
||||||
void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
|
void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
|
||||||
{
|
{
|
||||||
SUB(Rd, Rn, Rm, ArithOption(Rd));
|
EncodeArithmeticInst(1, false, Rd, Rn, Rm, ArithOption(Rd));
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
|
void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
|
||||||
|
|
Loading…
Reference in New Issue