Adding MMU state values to state
because that allow the MMU state to be loaded
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@ -598,9 +598,6 @@ union UPTE2
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u32 Hex;
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};
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u32 pagetable_base = 0;
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u32 pagetable_hashmask = 0;
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void GenerateDSIException(u32 _EffectiveAddress, bool _bWrite)
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{
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if (_bWrite)
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@ -644,8 +641,8 @@ void SDRUpdated()
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{
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return;
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}
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pagetable_base = htaborg<<16;
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pagetable_hashmask = ((xx<<10)|0x3ff);
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PowerPC::ppcState.pagetable_base = htaborg<<16;
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PowerPC::ppcState.pagetable_hashmask = ((xx<<10)|0x3ff);
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}
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@ -821,7 +818,7 @@ u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
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// hash function no 1 "xor" .360
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u32 hash1 = (VSID ^ page_index);
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u32 pteg_addr = ((hash1 & pagetable_hashmask) << 6) | pagetable_base;
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u32 pteg_addr = ((hash1 & PowerPC::ppcState.pagetable_hashmask) << 6) | PowerPC::ppcState.pagetable_base;
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// hash1
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for (int i = 0; i < 8; i++)
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@ -856,7 +853,7 @@ u32 TranslatePageAddress(const u32 _Address, const XCheckTLBFlag _Flag)
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// hash function no 2 "not" .360
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hash1 = ~hash1;
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pteg_addr = ((hash1 & pagetable_hashmask) << 6) | pagetable_base;
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pteg_addr = ((hash1 & PowerPC::ppcState.pagetable_hashmask) << 6) | PowerPC::ppcState.pagetable_base;
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for (int i = 0; i < 8; i++)
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{
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u32 pte = bswap(*(u32*)&pRAM[pteg_addr]);
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@ -138,6 +138,8 @@ void Init(int cpu_core)
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ppcState.itlb_last = 0;
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memset(ppcState.itlb_va, 0, sizeof(ppcState.itlb_va));
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memset(ppcState.itlb_pa, 0, sizeof(ppcState.itlb_pa));
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ppcState.pagetable_base = 0;
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ppcState.pagetable_hashmask = 0;
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ResetRegisters();
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PPCTables::InitTables(cpu_core);
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@ -64,6 +64,9 @@ struct GC_ALIGNED64(PowerPCState)
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u32 itlb_va[128];
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u32 itlb_pa[128];
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u32 pagetable_base;
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u32 pagetable_hashmask;
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InstructionCache iCache;
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};
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@ -59,7 +59,7 @@ static Common::Event g_compressAndDumpStateSyncEvent;
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static std::thread g_save_thread;
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// Don't forget to increase this after doing changes on the savestate system
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static const u32 STATE_VERSION = 18;
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static const u32 STATE_VERSION = 19;
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enum
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{
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