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Merge pull request #8551 from Sintendo/jit64addx 

Jit64: addx optimizations
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Tilka 2020-01-06 13:15:17 +01:00 committed by GitHub
parent 6e18dfb600 12fcbac2a3
commit f17f03ea3c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 15 additions and 4 deletions
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19
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -1330,18 +1330,29 @@ void Jit64::addx(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write); RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rb, Rd); RegCache::Realize(Ra, Rb, Rd);
if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE) if (d == a)
{ {
LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg())); ADD(32, Rd, Rb);
} }
else if (d == b) else if (d == b)
{ {
ADD(32, Rd, Ra); ADD(32, Rd, Ra);
} }
else if (Ra.IsSimpleReg() && Rb.IsSimpleReg() && !inst.OE)
{
LEA(32, Rd, MRegSum(Ra.GetSimpleReg(), Rb.GetSimpleReg()));
}
else if (Ra.IsSimpleReg() && Rb.IsImm() && !inst.OE)
{
LEA(32, Rd, MDisp(Ra.GetSimpleReg(), Rb.SImm32()));
}
else if (Rb.IsSimpleReg() && Ra.IsImm() && !inst.OE)
{
LEA(32, Rd, MDisp(Rb.GetSimpleReg(), Ra.SImm32()));
}
else else
{ {
if (d != a) MOV(32, Rd, Ra);
MOV(32, Rd, Ra);
ADD(32, Rd, Rb); ADD(32, Rd, Rb);
} }
if (inst.OE) if (inst.OE)