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Merge pull request #6335 from stenzek/membp 

Jit64: Fix incorrect PC in PPC state during fastmem trampoline
This commit is contained in:
Markus Wick 2018-02-15 11:13:52 +01:00 committed by GitHub
parent dff7837715 15efd42eba
commit e7d0aae5be
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 8 additions and 7 deletions
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4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
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@ -923,10 +923,6 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc
fprToFlush[js.revertFprLoad] = false; fprToFlush[js.revertFprLoad] = false;
gpr.Flush(RegCache::FlushMode::MaintainState, gprToFlush); gpr.Flush(RegCache::FlushMode::MaintainState, gprToFlush);
fpr.Flush(RegCache::FlushMode::MaintainState, fprToFlush); fpr.Flush(RegCache::FlushMode::MaintainState, fprToFlush);
// If a memory exception occurs, the exception handler will read
// from PC. Update PC with the latest value in case that happens.
MOV(32, PPCSTATE(pc), Imm32(ops[i].address));
WriteExceptionExit(); WriteExceptionExit();
SwitchToNearCode(); SwitchToNearCode();
} }

7
Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
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@ -376,6 +376,10 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress,
exit = J(true); exit = J(true);
SetJumpTarget(slow); SetJumpTarget(slow);
} }
// Helps external systems know which instruction triggered the read.
MOV(32, PPCSTATE(pc), Imm32(g_jit->js.compilerPC));
size_t rsp_alignment = (flags & SAFE_LOADSTORE_NO_PROLOG) ? 8 : 0; size_t rsp_alignment = (flags & SAFE_LOADSTORE_NO_PROLOG) ? 8 : 0;
ABI_PushRegistersAndAdjustStack(registersInUse, rsp_alignment); ABI_PushRegistersAndAdjustStack(registersInUse, rsp_alignment);
switch (accessSize) switch (accessSize)
@ -436,6 +440,9 @@ void EmuCodeBlock::SafeLoadToRegImmediate(X64Reg reg_value, u32 address, int acc
return; return;
} }
// Helps external systems know which instruction triggered the read.
MOV(32, PPCSTATE(pc), Imm32(g_jit->js.compilerPC));
// Fall back to general-case code. // Fall back to general-case code.
ABI_PushRegistersAndAdjustStack(registersInUse, 0); ABI_PushRegistersAndAdjustStack(registersInUse, 0);
switch (accessSize) switch (accessSize)

1
Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp
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@ -70,6 +70,7 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx)
js.generatingTrampoline = true; js.generatingTrampoline = true;
js.trampolineExceptionHandler = exceptionHandler; js.trampolineExceptionHandler = exceptionHandler;
js.compilerPC = info.pc;
// Generate the trampoline. // Generate the trampoline.
const u8* trampoline = trampolines.GenerateTrampoline(info); const u8* trampoline = trampolines.GenerateTrampoline(info);

3
Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp
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@ -63,9 +63,6 @@ const u8* TrampolineCache::GenerateWriteTrampoline(const TrampolineInfo& info)
// Don't treat FIFO writes specially for now because they require a burst // Don't treat FIFO writes specially for now because they require a burst
// check anyway. // check anyway.
// PC is used by memory watchpoints (if enabled) or to print accurate PC locations in debug logs
MOV(32, PPCSTATE(pc), Imm32(info.pc));
SafeWriteRegToReg(info.op_arg, info.op_reg, info.accessSize << 3, info.offset, SafeWriteRegToReg(info.op_arg, info.op_reg, info.accessSize << 3, info.offset,
info.registersInUse, info.flags | SAFE_LOADSTORE_FORCE_SLOWMEM); info.registersInUse, info.flags | SAFE_LOADSTORE_FORCE_SLOWMEM);