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Core: Pass several parameters by const reference

This commit is contained in:
Lioncash 2015-06-04 14:06:22 -04:00
parent 98ed5881ab
commit d9b51f74be
9 changed files with 16 additions and 16 deletions
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2
Source/Core/Core/ARDecrypt.cpp
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@ -414,7 +414,7 @@ static int GetVal(const char *flt, char chr)
return ret; return ret;
} }
static int alphatobin(u32 *dst, std::vector<std::string> alpha, int size) static int alphatobin(u32 *dst, const std::vector<std::string>& alpha, int size)
{ {
int j = 0; int j = 0;
int ret = 0; int ret = 0;

6
Source/Core/Core/DSP/DSPEmitter.h
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@ -272,11 +272,11 @@ private:
void round_long_acc(Gen::X64Reg long_acc = Gen::EAX); void round_long_acc(Gen::X64Reg long_acc = Gen::EAX);
void set_long_acc(int _reg, Gen::X64Reg acc = Gen::EAX); void set_long_acc(int _reg, Gen::X64Reg acc = Gen::EAX);
void get_acc_h(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true); void get_acc_h(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true);
void set_acc_h(int _reg, Gen::OpArg arg = R(Gen::EAX)); void set_acc_h(int _reg, const Gen::OpArg& arg = R(Gen::EAX));
void get_acc_m(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true); void get_acc_m(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true);
void set_acc_m(int _reg, Gen::OpArg arg = R(Gen::EAX)); void set_acc_m(int _reg, const Gen::OpArg& arg = R(Gen::EAX));
void get_acc_l(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true); void get_acc_l(int _reg, Gen::X64Reg acc = Gen::EAX, bool sign = true);
void set_acc_l(int _reg, Gen::OpArg arg = R(Gen::EAX)); void set_acc_l(int _reg, const Gen::OpArg& arg = R(Gen::EAX));
void get_long_acx(int _reg, Gen::X64Reg acx = Gen::EAX); void get_long_acx(int _reg, Gen::X64Reg acx = Gen::EAX);
void get_ax_l(int _reg, Gen::X64Reg acx = Gen::EAX); void get_ax_l(int _reg, Gen::X64Reg acx = Gen::EAX);
void get_ax_h(int _reg, Gen::X64Reg acc = Gen::EAX); void get_ax_h(int _reg, Gen::X64Reg acc = Gen::EAX);

6
Source/Core/Core/DSP/Jit/DSPJitUtil.cpp
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@ -763,7 +763,7 @@ void DSPEmitter::get_acc_l(int _reg, X64Reg acl, bool sign)
gpr.readReg(_reg+DSP_REG_ACL0, acl, sign?SIGN:ZERO); gpr.readReg(_reg+DSP_REG_ACL0, acl, sign?SIGN:ZERO);
} }
void DSPEmitter::set_acc_l(int _reg, OpArg arg) void DSPEmitter::set_acc_l(int _reg, const OpArg& arg)
{ {
// return g_dsp.r[DSP_REG_ACM0 + _reg]; // return g_dsp.r[DSP_REG_ACM0 + _reg];
gpr.writeReg(_reg+DSP_REG_ACL0,arg); gpr.writeReg(_reg+DSP_REG_ACL0,arg);
@ -777,7 +777,7 @@ void DSPEmitter::get_acc_m(int _reg, X64Reg acm, bool sign)
} }
// In: s16 in AX // In: s16 in AX
void DSPEmitter::set_acc_m(int _reg, OpArg arg) void DSPEmitter::set_acc_m(int _reg, const OpArg& arg)
{ {
// return g_dsp.r.ac[_reg].m; // return g_dsp.r.ac[_reg].m;
gpr.writeReg(_reg+DSP_REG_ACM0,arg); gpr.writeReg(_reg+DSP_REG_ACM0,arg);
@ -791,7 +791,7 @@ void DSPEmitter::get_acc_h(int _reg, X64Reg ach, bool sign)
} }
// In: s16 in AX // In: s16 in AX
void DSPEmitter::set_acc_h(int _reg, OpArg arg) void DSPEmitter::set_acc_h(int _reg, const OpArg& arg)
{ {
// return g_dsp.r[DSP_REG_ACM0 + _reg]; // return g_dsp.r[DSP_REG_ACM0 + _reg];
gpr.writeReg(_reg+DSP_REG_ACH0,arg); gpr.writeReg(_reg+DSP_REG_ACH0,arg);

2
Source/Core/Core/GeckoCode.cpp
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@ -33,7 +33,7 @@ bool GeckoCode::Exist(u32 address, u32 data) const
} }
// return true if the code is identical // return true if the code is identical
bool GeckoCode::Compare(GeckoCode compare) const bool GeckoCode::Compare(const GeckoCode& compare) const
{ {
if (codes.size() != compare.codes.size()) if (codes.size() != compare.codes.size())
return false; return false;

2
Source/Core/Core/GeckoCode.h
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@ -36,7 +36,7 @@ namespace Gecko
bool enabled; bool enabled;
bool user_defined; bool user_defined;
bool Compare(GeckoCode compare) const; bool Compare(const GeckoCode& compare) const;
bool Exist(u32 address, u32 data) const; bool Exist(u32 address, u32 data) const;
}; };

2
Source/Core/Core/HW/GCMemcard.cpp
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@ -347,7 +347,7 @@ u16 GCMemcard::GetFreeBlocks() const
return BE16(CurrentBat->FreeBlocks); return BE16(CurrentBat->FreeBlocks);
} }
u8 GCMemcard::TitlePresent(DEntry d) const u8 GCMemcard::TitlePresent(const DEntry& d) const
{ {
if (!m_valid) if (!m_valid)
return DIRLEN; return DIRLEN;

2
Source/Core/Core/HW/GCMemcard.h
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@ -360,7 +360,7 @@ public:
u16 GetFreeBlocks() const; u16 GetFreeBlocks() const;
// If title already on memcard returns index, otherwise returns -1 // If title already on memcard returns index, otherwise returns -1
u8 TitlePresent(DEntry d) const; u8 TitlePresent(const DEntry& d) const;
bool GCI_FileName(u8 index, std::string &filename) const; bool GCI_FileName(u8 index, std::string &filename) const;
// DEntry functions, all take u8 index < DIRLEN (127) // DEntry functions, all take u8 index < DIRLEN (127)

4
Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
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@ -347,7 +347,7 @@ void GPRRegCache::LoadRegister(size_t preg, X64Reg newLoc)
emit->MOV(32, ::Gen::R(newLoc), regs[preg].location); emit->MOV(32, ::Gen::R(newLoc), regs[preg].location);
} }
void GPRRegCache::StoreRegister(size_t preg, OpArg newLoc) void GPRRegCache::StoreRegister(size_t preg, const OpArg& newLoc)
{ {
emit->MOV(32, newLoc, regs[preg].location); emit->MOV(32, newLoc, regs[preg].location);
} }
@ -357,7 +357,7 @@ void FPURegCache::LoadRegister(size_t preg, X64Reg newLoc)
emit->MOVAPD(newLoc, regs[preg].location); emit->MOVAPD(newLoc, regs[preg].location);
} }
void FPURegCache::StoreRegister(size_t preg, OpArg newLoc) void FPURegCache::StoreRegister(size_t preg, const OpArg& newLoc)
{ {
emit->MOVAPD(newLoc, regs[preg].location.GetSimpleReg()); emit->MOVAPD(newLoc, regs[preg].location.GetSimpleReg());
} }

6
Source/Core/Core/PowerPC/Jit64/JitRegCache.h
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@ -90,7 +90,7 @@ public:
//read only will not set dirty flag //read only will not set dirty flag
void BindToRegister(size_t preg, bool doLoad = true, bool makeDirty = true); void BindToRegister(size_t preg, bool doLoad = true, bool makeDirty = true);
void StoreFromRegister(size_t preg, FlushMode mode = FLUSH_ALL); void StoreFromRegister(size_t preg, FlushMode mode = FLUSH_ALL);
virtual void StoreRegister(size_t preg, Gen::OpArg newLoc) = 0; virtual void StoreRegister(size_t preg, const Gen::OpArg& newLoc) = 0;
virtual void LoadRegister(size_t preg, Gen::X64Reg newLoc) = 0; virtual void LoadRegister(size_t preg, Gen::X64Reg newLoc) = 0;
const Gen::OpArg &R(size_t preg) const const Gen::OpArg &R(size_t preg) const
@ -159,7 +159,7 @@ public:
class GPRRegCache : public RegCache class GPRRegCache : public RegCache
{ {
public: public:
void StoreRegister(size_t preg, Gen::OpArg newLoc) override; void StoreRegister(size_t preg, const Gen::OpArg& newLoc) override;
void LoadRegister(size_t preg, Gen::X64Reg newLoc) override; void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
Gen::OpArg GetDefaultLocation(size_t reg) const override; Gen::OpArg GetDefaultLocation(size_t reg) const override;
const int* GetAllocationOrder(size_t& count) override; const int* GetAllocationOrder(size_t& count) override;
@ -172,7 +172,7 @@ public:
class FPURegCache : public RegCache class FPURegCache : public RegCache
{ {
public: public:
void StoreRegister(size_t preg, Gen::OpArg newLoc) override; void StoreRegister(size_t preg, const Gen::OpArg& newLoc) override;
void LoadRegister(size_t preg, Gen::X64Reg newLoc) override; void LoadRegister(size_t preg, Gen::X64Reg newLoc) override;
const int* GetAllocationOrder(size_t& count) override; const int* GetAllocationOrder(size_t& count) override;
Gen::OpArg GetDefaultLocation(size_t reg) const override; Gen::OpArg GetDefaultLocation(size_t reg) const override;