IPC: Fix missing interrupt when writing to Y1/Y2
The IPC interrupt is triggered when IY1/IY2 is set and Y1/Y2 is written to even when this results in clearing the bit. This shouldn't change anything in practice but it's a difference that Dolphin wasn't taking into account, which made me waste some time when I was writing a hwtest :/
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@ -153,6 +153,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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mmio->Register(base | IPC_PPCCTRL, MMIO::ComplexRead<u32>([](u32) { return ctrl.ppc(); }),
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MMIO::ComplexWrite<u32>([](u32, u32 val) {
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ctrl.ppc(val);
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// The IPC interrupt is triggered when IY1/IY2 is set and
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// Y1/Y2 is written to -- even when this results in clearing the bit.
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if ((val >> 2 & 1 && ctrl.IY1) || (val >> 1 & 1 && ctrl.IY2))
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ppc_irq_flags |= INT_CAUSE_IPC_BROADWAY;
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if (ctrl.X1)
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HLE::GetIOS()->EnqueueIPCRequest(ppc_msg);
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HLE::GetIOS()->UpdateIPC();
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