From b9f7d67667643bb237c313cbd80f3a688f5a04a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?L=C3=A9o=20Lam?= Date: Tue, 27 Feb 2018 15:57:07 +0100 Subject: [PATCH] IPC: Fix missing interrupt when writing to Y1/Y2 The IPC interrupt is triggered when IY1/IY2 is set and Y1/Y2 is written to even when this results in clearing the bit. This shouldn't change anything in practice but it's a difference that Dolphin wasn't taking into account, which made me waste some time when I was writing a hwtest :/ --- Source/Core/Core/HW/WII_IPC.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Source/Core/Core/HW/WII_IPC.cpp b/Source/Core/Core/HW/WII_IPC.cpp index ca5b15d7bf..3ba154b46d 100644 --- a/Source/Core/Core/HW/WII_IPC.cpp +++ b/Source/Core/Core/HW/WII_IPC.cpp @@ -153,6 +153,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base) mmio->Register(base | IPC_PPCCTRL, MMIO::ComplexRead([](u32) { return ctrl.ppc(); }), MMIO::ComplexWrite([](u32, u32 val) { ctrl.ppc(val); + // The IPC interrupt is triggered when IY1/IY2 is set and + // Y1/Y2 is written to -- even when this results in clearing the bit. + if ((val >> 2 & 1 && ctrl.IY1) || (val >> 1 & 1 && ctrl.IY2)) + ppc_irq_flags |= INT_CAUSE_IPC_BROADWAY; if (ctrl.X1) HLE::GetIOS()->EnqueueIPCRequest(ppc_msg); HLE::GetIOS()->UpdateIPC();