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JIT: fix register preloading 

Partially broken by typoes in the bitset patch.
This commit is contained in:
Fiora 2014-11-04 04:50:05 -08:00
parent 75df11335a
commit b81686b582
1 changed files with 2 additions and 2 deletions
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4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
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@ -747,12 +747,12 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm()) if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm())
gpr.BindToRegister(reg, true, false); gpr.BindToRegister(reg, true, false);
} }
for (int reg : ops[i].regsOut) for (int reg : ops[i].fregsIn)
{ {
if (fpr.NumFreeRegisters() < 2) if (fpr.NumFreeRegisters() < 2)
break; break;
if (ops[i].fprInXmm[reg]) if (ops[i].fprInXmm[reg])
gpr.BindToRegister(reg, true, false); fpr.BindToRegister(reg, true, false);
} }
Jit64Tables::CompileInstruction(ops[i]); Jit64Tables::CompileInstruction(ops[i]);