From b81686b582b41787ff6441e70d61ea7f1e1e7f0d Mon Sep 17 00:00:00 2001
From: Fiora <fioraaeterna@gmail.com>
Date: Tue, 4 Nov 2014 04:50:05 -0800
Subject: [PATCH] JIT: fix register preloading

Partially broken by typoes in the bitset patch.
---
 Source/Core/Core/PowerPC/Jit64/Jit.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp
index 2294dbcfb0..8de45ae981 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp
@@ -747,12 +747,12 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc
 				if (ops[i].gprInReg[reg] && !gpr.R(reg).IsImm())
 					gpr.BindToRegister(reg, true, false);
 			}
-			for (int reg : ops[i].regsOut)
+			for (int reg : ops[i].fregsIn)
 			{
 				if (fpr.NumFreeRegisters() < 2)
 					break;
 				if (ops[i].fprInXmm[reg])
-					gpr.BindToRegister(reg, true, false);
+					fpr.BindToRegister(reg, true, false);
 			}
 
 			Jit64Tables::CompileInstruction(ops[i]);