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Add conditional register cache flushing to JIT64's twx instruction.

This commit is contained in:
Ryan Houdek 2014-06-10 02:46:10 -05:00
parent 06e8c7d7c9
commit b4ec70f0ac
1 changed files with 4 additions and 3 deletions
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7
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -2182,9 +2182,6 @@ void Jit64::twx(UGeckoInstruction inst)
s32 a = inst.RA; s32 a = inst.RA;
gpr.Flush();
fpr.Flush();
if (inst.OPCD == 3) // twi if (inst.OPCD == 3) // twi
CMP(32, gpr.R(a), gpr.R(inst.RB)); CMP(32, gpr.R(a), gpr.R(inst.RB));
else // tw else // tw
@ -2209,6 +2206,10 @@ void Jit64::twx(UGeckoInstruction inst)
} }
LOCK(); LOCK();
OR(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_PROGRAM)); OR(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_PROGRAM));
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
WriteExceptionExit(); WriteExceptionExit();
SetJumpTarget(dont_trap); SetJumpTarget(dont_trap);