From b4ec70f0ac7fe8a527227bb21554c8893dfbffa9 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Tue, 10 Jun 2014 02:46:10 -0500 Subject: [PATCH] Add conditional register cache flushing to JIT64's twx instruction. --- Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp index 228fd78929..91eb133c36 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp @@ -2182,9 +2182,6 @@ void Jit64::twx(UGeckoInstruction inst) s32 a = inst.RA; - gpr.Flush(); - fpr.Flush(); - if (inst.OPCD == 3) // twi CMP(32, gpr.R(a), gpr.R(inst.RB)); else // tw @@ -2209,6 +2206,10 @@ void Jit64::twx(UGeckoInstruction inst) } LOCK(); OR(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_PROGRAM)); + + gpr.Flush(FLUSH_MAINTAIN_STATE); + fpr.Flush(FLUSH_MAINTAIN_STATE); + WriteExceptionExit(); SetJumpTarget(dont_trap);