LLE Recommit some clean up from previous commits
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3652 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -143,8 +143,8 @@ u16 dsp_read_accelerator()
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Address = (gdsp_ifx_regs[DSP_ACSAH] << 16) | gdsp_ifx_regs[DSP_ACSAL];
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Address = (gdsp_ifx_regs[DSP_ACSAH] << 16) | gdsp_ifx_regs[DSP_ACSAL];
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// Do we really need both?
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// Do we really need both?
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DSPCore_SetException(3);
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DSPCore_SetException(EXP_4);
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DSPCore_SetException(5);
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DSPCore_SetException(EXP_ACCOV);
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// Somehow, YN1 and YN2 must be initialized with their "loop" values, so yeah,
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// Somehow, YN1 and YN2 must be initialized with their "loop" values, so yeah,
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// it seems likely that we should raise an exception to let the DSP program do that,
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// it seems likely that we should raise an exception to let the DSP program do that,
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@ -37,6 +37,7 @@ SDSP g_dsp;
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DSPBreakpoints dsp_breakpoints;
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DSPBreakpoints dsp_breakpoints;
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DSPCoreState core_state = DSPCORE_RUNNING;
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DSPCoreState core_state = DSPCORE_RUNNING;
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Common::Event step_event;
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Common::Event step_event;
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DSPInitialize *dsp_initialize = NULL;
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static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
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static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
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{
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{
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@ -64,8 +65,10 @@ static bool LoadRom(const char *fname, int size_in_words, u16 *rom)
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return false;
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return false;
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}
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}
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename)
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename, DSPInitialize *dspInit)
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{
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{
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dsp_initialize = dspInit;
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g_dsp.step_counter = 0;
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g_dsp.step_counter = 0;
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g_dsp.irom = (u16*)AllocateMemoryPages(DSP_IROM_BYTE_SIZE);
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g_dsp.irom = (u16*)AllocateMemoryPages(DSP_IROM_BYTE_SIZE);
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@ -157,10 +160,10 @@ void DSPCore_CheckExternalInterrupt()
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// check if there is an external interrupt
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// check if there is an external interrupt
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if (g_dsp.cr & CR_EXTERNAL_INT)
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if (g_dsp.cr & CR_EXTERNAL_INT)
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{
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{
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if (dsp_SR_is_flag_set(FLAG_ENABLE_INTERUPT) && (g_dsp.exception_in_progress_hack == false))
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if (dsp_SR_is_flag_set(SR_EXT_INT_ENABLE) && (g_dsp.exception_in_progress_hack == false))
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{
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{
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// level 7 is the interrupt exception
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// level 7 is the interrupt exception
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DSPCore_SetException(7);
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DSPCore_SetException(EXP_INT);
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g_dsp.cr &= ~CR_EXTERNAL_INT;
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g_dsp.cr &= ~CR_EXTERNAL_INT;
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}
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}
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@ -27,6 +27,7 @@
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#define _DSPCORE_H
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#define _DSPCORE_H
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#include "DSPBreakpoints.h"
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#include "DSPBreakpoints.h"
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#include "AudioCommon.h"
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#define DSP_IRAM_BYTE_SIZE 0x2000
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#define DSP_IRAM_BYTE_SIZE 0x2000
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#define DSP_IRAM_SIZE 0x1000
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#define DSP_IRAM_SIZE 0x1000
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@ -153,7 +154,7 @@
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#define SR_TOP2BITS 0x0020 // this is an odd one. (set by tst)
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#define SR_TOP2BITS 0x0020 // this is an odd one. (set by tst)
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#define SR_LOGIC_ZERO 0x0040
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#define SR_LOGIC_ZERO 0x0040
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#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
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#define SR_INT_ENABLE 0x0200 // Not 100% sure but duddie says so. This should replace the hack, if so.
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#define SR_800 0x0800 // Appears in zelda - what is it? where in the zelda ucode?
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#define SR_EXT_INT_ENABLE 0x0800 // Appears in zelda - seems to disable external interupts
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#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
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#define SR_MUL_MODIFY 0x2000 // 1 = normal. 0 = x2 (M0, M2)
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#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
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#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
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#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.
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#define SR_MUL_UNSIGNED 0x8000 // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats operands as unsigned. Tested with mulx only so far.
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@ -161,6 +162,15 @@
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// This should be the bits affected by CMP. Does not include logic zero.
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// This should be the bits affected by CMP. Does not include logic zero.
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#define SR_CMP_MASK 0x3f
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#define SR_CMP_MASK 0x3f
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// exceptions vector
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#define EXP_RESET 0 // 0x0000
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#define EXP_STOVF 1 // 0x0002 stack under/over flow
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#define EXP_4 2 // 0x0004
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#define EXP_6 3 // 0x0006
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#define EXP_8 4 // 0x0008
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#define EXP_ACCOV 5 // 0x000a accelerator address overflow
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#define EXP_c 6 // 0x000c
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#define EXP_INT 7 // 0x000e external int? (mail?)
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struct SDSP
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struct SDSP
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{
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{
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@ -202,8 +212,10 @@ struct SDSP
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extern SDSP g_dsp;
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extern SDSP g_dsp;
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extern DSPBreakpoints dsp_breakpoints;
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extern DSPBreakpoints dsp_breakpoints;
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extern DSPInitialize *dsp_initialize;
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename, DSPInitialize *dspInit = NULL);
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bool DSPCore_Init(const char *irom_filename, const char *coef_filename);
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void DSPCore_Reset();
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void DSPCore_Reset();
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void DSPCore_Shutdown(); // Frees all allocated memory.
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void DSPCore_Shutdown(); // Frees all allocated memory.
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@ -142,7 +142,7 @@ void gdsp_ifx_write(u16 addr, u16 val)
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break;
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break;
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case 0xd3: // ZeldaUnk (accelerator WRITE)
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case 0xd3: // ZeldaUnk (accelerator WRITE)
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ERROR_LOG(DSPLLE, "Write To ZeldaUnk pc=%04x (%04x)\n", g_dsp.pc, val);
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INFO_LOG(DSPLLE, "Write To ZeldaUnk pc=%04x (%04x)\n", g_dsp.pc, val);
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dsp_write_aram_d3(val);
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dsp_write_aram_d3(val);
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break;
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break;
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@ -38,12 +38,12 @@
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// ---------------------------------------------------------------------------------------
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// ---------------------------------------------------------------------------------------
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inline void dsp_SR_set_flag(int flag)
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inline void dsp_SR_set_flag(int flag)
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{
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{
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g_dsp.r[DSP_REG_SR] |= (1 << flag);
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g_dsp.r[DSP_REG_SR] |= flag;
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}
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}
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inline bool dsp_SR_is_flag_set(int flag)
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inline bool dsp_SR_is_flag_set(int flag)
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{
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{
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return (g_dsp.r[DSP_REG_SR] & (1 << flag)) != 0;
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return (g_dsp.r[DSP_REG_SR] & flag) != 0;
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}
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}
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@ -21,7 +21,6 @@
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#include "DSPTables.h"
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#include "DSPTables.h"
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#define DSP_REG_MASK 0x1f
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#define DSP_REG_MASK 0x1f
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#define FLAG_ENABLE_INTERUPT 11
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namespace DSPInterpreter {
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namespace DSPInterpreter {
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@ -48,8 +48,8 @@ void call(const UDSPInstruction& opc)
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// Generic callr implementation
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// Generic callr implementation
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// CALLRcc $R
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// CALLRcc $R
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// 0001 0111 rrr1 cccc
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// 0001 0111 rrr1 cccc
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// Call functionif condition cc has been met.Push program counter of
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// Call function if condition cc has been met. Push program counter of
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// instruction following "call" tocall stack $st0. Set program counter to
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// instruction following "call" to call stack $st0. Set program counter to
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// register $R.
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// register $R.
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void callr(const UDSPInstruction& opc)
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void callr(const UDSPInstruction& opc)
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{
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{
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@ -121,7 +121,6 @@ void ret(const UDSPInstruction& opc)
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// Return from exception. Pops stored status register $sr from data stack
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// Return from exception. Pops stored status register $sr from data stack
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// location.
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// location.
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// FIXME: is it also conditional? unknown opcodes 0x02fx
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void rti(const UDSPInstruction& opc)
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void rti(const UDSPInstruction& opc)
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{
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{
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g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
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g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
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@ -206,12 +206,14 @@ void Initialize(void *init)
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std::string irom_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_IROM;
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std::string irom_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_IROM;
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std::string coef_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_COEF;
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std::string coef_filename = File::GetSysDirectory() + GC_SYS_DIR + DIR_SEP + DSP_COEF;
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bCanWork = DSPCore_Init(irom_filename.c_str(), coef_filename.c_str());
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bCanWork = DSPCore_Init(irom_filename.c_str(), coef_filename.c_str(), &g_dspInitialize);
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g_dsp.cpu_ram = g_dspInitialize.pGetMemoryPointer(0);
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g_dsp.cpu_ram = g_dspInitialize.pGetMemoryPointer(0);
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DSPCore_Reset();
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DSPCore_Reset();
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if (!bCanWork)
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if (!bCanWork)
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{
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{
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PanicAlert("DSPLLE: Failed to initialize plugin, exiting");
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DSPCore_Shutdown();
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DSPCore_Shutdown();
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return;
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return;
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}
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}
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