Fixed the slowdown that occurred under JIT32. Fixes issue 4969.
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3d2a2abb49
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9eaf20cc44
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@ -265,7 +265,6 @@ inline void WriteToHardware(u32 em_address, const T data, u32 effective_address,
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((em_address & 0xF0000000) == 0xC0000000) ||
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((em_address & 0xF0000000) == 0x00000000))
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{
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PowerPC::ppcState.iCache.InvalidateBlock(em_address);
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*(T*)&m_pRAM[em_address & RAM_MASK] = bswap(data);
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return;
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}
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@ -273,7 +272,6 @@ inline void WriteToHardware(u32 em_address, const T data, u32 effective_address,
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((em_address & 0xF0000000) == 0xD0000000) ||
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((em_address & 0xF0000000) == 0x10000000))
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{
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PowerPC::ppcState.iCache.InvalidateBlock(em_address);
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*(T*)&m_pEXRAM[em_address & EXRAM_MASK] = bswap(data);
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return;
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}
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@ -286,7 +284,6 @@ inline void WriteToHardware(u32 em_address, const T data, u32 effective_address,
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(bFakeVMEM && ((em_address &0xF0000000) == 0x40000000)))
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{
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// fake VMEM
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PowerPC::ppcState.iCache.InvalidateBlock(em_address);
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*(T*)&m_pFakeVMEM[em_address & FAKEVMEM_MASK] = bswap(data);
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}
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else
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@ -103,12 +103,6 @@ namespace PowerPC
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jit->GetBlockCache()->InvalidateICache(addr);
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}
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void InstructionCache::InvalidateBlock(u32 addr)
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{
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if (jit)
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jit->GetBlockCache()->InvalidateICache(addr);
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}
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u32 InstructionCache::ReadInstruction(u32 addr)
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{
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if (!HID0.ICE) // instruction cache is disabled
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@ -53,7 +53,6 @@ namespace PowerPC
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void Reset();
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u32 ReadInstruction(u32 addr);
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void Invalidate(u32 addr);
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void InvalidateBlock(u32 addr);
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};
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}
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