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Allow runtime setting of fastmem in ARM and disable since it seems to be causing issues again. Cortex-A9 only?

This commit is contained in:
Ryan Houdek 2013-04-20 17:36:49 +00:00
parent 05eda7b0c1
commit 9720d6b418
1 changed files with 127 additions and 108 deletions
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235
Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStore.cpp
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@ -34,7 +34,7 @@
#ifdef ANDROID #ifdef ANDROID
#define FASTMEM 0 #define FASTMEM 0
#else #else
#define FASTMEM 1 #define FASTMEM 0
#endif #endif
void JitArm::stbu(UGeckoInstruction inst) void JitArm::stbu(UGeckoInstruction inst)
{ {
@ -156,45 +156,50 @@ void JitArm::stw(UGeckoInstruction inst)
ARMReg RS = gpr.R(inst.RS); ARMReg RS = gpr.R(inst.RS);
#if FASTMEM #if FASTMEM
// R10 contains the dest address // R10 contains the dest address
ARMReg Value = R11; if (Core::g_CoreStartupParameter.bFastmem)
ARMReg RA;
if (inst.RA)
RA = gpr.R(inst.RA);
MOV(Value, RS);
if (inst.RA)
{ {
MOVI2R(R10, inst.SIMM_16, false); ARMReg Value = R11;
ADD(R10, R10, RA); ARMReg RA;
if (inst.RA)
RA = gpr.R(inst.RA);
MOV(Value, RS);
if (inst.RA)
{
MOVI2R(R10, inst.SIMM_16, false);
ADD(R10, R10, RA);
}
else
{
MOVI2R(R10, (u32)inst.SIMM_16, false);
NOP(1);
}
StoreFromReg(R10, Value, 32, 0);
} }
else else
{
MOVI2R(R10, (u32)inst.SIMM_16, false);
NOP(1);
}
StoreFromReg(R10, Value, 32, 0);
#else
ARMReg ValueReg = gpr.GetReg();
ARMReg Addr = gpr.GetReg();
ARMReg Function = gpr.GetReg();
MOV(ValueReg, RS);
if (inst.RA)
{
MOVI2R(Addr, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(Addr, Addr, RA);
}
else
MOVI2R(Addr, (u32)inst.SIMM_16);
MOVI2R(Function, (u32)&Memory::Write_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, ValueReg);
MOV(R1, Addr);
BL(Function);
POP(4, R0, R1, R2, R3);
gpr.Unlock(ValueReg, Addr, Function);
#endif #endif
{
ARMReg ValueReg = gpr.GetReg();
ARMReg Addr = gpr.GetReg();
ARMReg Function = gpr.GetReg();
MOV(ValueReg, RS);
if (inst.RA)
{
MOVI2R(Addr, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(Addr, Addr, RA);
}
else
MOVI2R(Addr, (u32)inst.SIMM_16);
MOVI2R(Function, (u32)&Memory::Write_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, ValueReg);
MOV(R1, Addr);
BL(Function);
POP(4, R0, R1, R2, R3);
gpr.Unlock(ValueReg, Addr, Function);
}
} }
void JitArm::stwu(UGeckoInstruction inst) void JitArm::stwu(UGeckoInstruction inst)
{ {
@ -316,35 +321,39 @@ void JitArm::lbz(UGeckoInstruction inst)
// Backpatch route // Backpatch route
// Gets loaded in to RD // Gets loaded in to RD
// Address is in R10 // Address is in R10
gpr.Unlock(rA, rB); if (Core::g_CoreStartupParameter.bFastmem)
if (inst.RA)
{ {
ARMReg RA = gpr.R(inst.RA); gpr.Unlock(rA, rB);
MOV(R10, RA); // - 4 if (inst.RA)
{
ARMReg RA = gpr.R(inst.RA);
MOV(R10, RA); // - 4
}
else
MOV(R10, 0); // - 4
LoadToReg(RD, R10, 8, inst.SIMM_16);
} }
else else
MOV(R10, 0); // - 4
LoadToReg(RD, R10, 8, inst.SIMM_16);
#else
if (inst.RA)
{
MOVI2R(rB, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(rB, rB, RA);
}
else
MOVI2R(rB, (u32)inst.SIMM_16);
MOVI2R(rA, (u32)&Memory::Read_U8);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
#endif #endif
{
if (inst.RA)
{
MOVI2R(rB, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(rB, rB, RA);
}
else
MOVI2R(rB, (u32)inst.SIMM_16);
MOVI2R(rA, (u32)&Memory::Read_U8);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
}
SetJumpTarget(DoNotLoad); SetJumpTarget(DoNotLoad);
} }
@ -411,34 +420,39 @@ void JitArm::lwz(UGeckoInstruction inst)
// Backpatch route // Backpatch route
// Gets loaded in to RD // Gets loaded in to RD
// Address is in R10 // Address is in R10
gpr.Unlock(rA, rB); if (Core::g_CoreStartupParameter.bFastmem)
if (inst.RA)
{ {
ARMReg RA = gpr.R(inst.RA); gpr.Unlock(rA, rB);
MOV(R10, RA); // - 4 if (inst.RA)
{
ARMReg RA = gpr.R(inst.RA);
MOV(R10, RA); // - 4
}
else
MOV(R10, 0); // - 4
LoadToReg(RD, R10, 32, (u32)inst.SIMM_16);
} }
else else
MOV(R10, 0); // - 4
LoadToReg(RD, R10, 32, (u32)inst.SIMM_16);
#else
if (inst.RA)
{
MOVI2R(rB, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(rB, rB, RA);
}
else
MOVI2R(rB, (u32)inst.SIMM_16);
MOVI2R(rA, (u32)&Memory::Read_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
#endif #endif
{
if (inst.RA)
{
MOVI2R(rB, inst.SIMM_16);
ARMReg RA = gpr.R(inst.RA);
ADD(rB, rB, RA);
}
else
MOVI2R(rB, (u32)inst.SIMM_16);
MOVI2R(rA, (u32)&Memory::Read_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
}
SetJumpTarget(DoNotLoad); SetJumpTarget(DoNotLoad);
if (SConfig::GetInstance().m_LocalCoreStartupParameter.bSkipIdle && if (SConfig::GetInstance().m_LocalCoreStartupParameter.bSkipIdle &&
(inst.hex & 0xFFFF0000) == 0x800D0000 && (inst.hex & 0xFFFF0000) == 0x800D0000 &&
@ -484,33 +498,38 @@ void JitArm::lwzx(UGeckoInstruction inst)
// Backpatch route // Backpatch route
// Gets loaded in to RD // Gets loaded in to RD
// Address is in R10 // Address is in R10
gpr.Unlock(rA, rB); if (Core::g_CoreStartupParameter.bFastmem)
if (inst.RA)
{ {
ARMReg RA = gpr.R(inst.RA); gpr.Unlock(rA, rB);
ADD(R10, RA, RB); // - 4 if (inst.RA)
{
ARMReg RA = gpr.R(inst.RA);
ADD(R10, RA, RB); // - 4
}
else
MOV(R10, RB); // -4
LoadToReg(RD, R10, 32, 0);
} }
else else
MOV(R10, RB); // -4
LoadToReg(RD, R10, 32, 0);
#else
if (inst.RA)
{
ARMReg RA = gpr.R(inst.RA);
ADD(rB, RA, RB);
}
else
MOV(rB, RB);
MOVI2R(rA, (u32)&Memory::Read_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
#endif #endif
{
if (inst.RA)
{
ARMReg RA = gpr.R(inst.RA);
ADD(rB, RA, RB);
}
else
MOV(rB, RB);
MOVI2R(rA, (u32)&Memory::Read_U32);
PUSH(4, R0, R1, R2, R3);
MOV(R0, rB);
BL(rA);
MOV(rA, R0);
POP(4, R0, R1, R2, R3);
MOV(RD, rA);
gpr.Unlock(rA, rB);
}
SetJumpTarget(DoNotLoad); SetJumpTarget(DoNotLoad);
//// u32 temp = Memory::Read_U32(_inst.RA ? (m_GPR[_inst.RA] + m_GPR[_inst.RB]) : m_GPR[_inst.RB]); //// u32 temp = Memory::Read_U32(_inst.RA ? (m_GPR[_inst.RA] + m_GPR[_inst.RB]) : m_GPR[_inst.RB]);
} }