[ARM] Reenable flush per instruction with FPR cache. Something is still very wrong.

2013-09-19 02:08:10 +00:00 · 2013-09-19 02:08:10 +00:00 · 85f067780a
parent 930f997f04
commit 85f067780a
1 changed files with 1 additions and 0 deletions
--- a/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/Jit.cpp
@ -483,6 +483,7 @@ const u8* JitArm::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBlo
 					BKPT(0x7777);
 				}
 				JitArmTables::CompileInstruction(ops[i]);
+				fpr.Flush();
 				if (js.memcheck && (opinfo->flags & FL_LOADSTORE))
 				{
 					// Don't do this yet